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1. Datasheet
2. Getting Started with the Avalon-MM DMA
3. Parameter Settings
4. Physical Layout
5. Registers
6. Error Handling
7. PCI Express Protocol Stack
8. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-MM DMA for PCI Express
9. Design Implementation
A. Transaction Layer Packet (TLP) Header Formats
B. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-MM DMA Interface for PCIe Solutions User Guide Archive
C. Document Revision History
1.1. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-MM DMA Interface for PCIe* Datasheet
1.2. Features
1.3. Comparison of Avalon-ST, Avalon-MM and Avalon-MM with DMA Interfaces
1.4. Release Information
1.5. Device Family Support
1.6. Design Examples
1.7. IP Core Verification
1.8. Resource Utilization
1.9. Recommended Speed Grades
1.10. Creating a Design for PCI Express
3.1. Parameters
3.2. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-MM Settings
3.3. Base Address Register (BAR) Settings
3.4. Device Identification Registers
3.5. PCI Express and PCI Capabilities Parameters
3.6. Configuration, Debug, and Extension Options
3.7. PHY Characteristics
3.8. Example Designs
4.1. Hard IP Block Placement In Intel® Cyclone® 10 GX Devices
4.2. Hard IP Block Placement In Intel® Arria® 10 Devices
4.3. Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data Rates
4.4. Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate
4.5. PCI Express Gen3 Bank Usage Restrictions
5.1. Correspondence between Configuration Space Registers and the PCIe Specification
5.2. Type 0 Configuration Space Registers
5.3. Type 1 Configuration Space Registers
5.4. PCI Express Capability Structures
5.5. Intel-Defined VSEC Registers
5.6. Advanced Error Reporting Capability
5.7. DMA Descriptor Controller Registers
5.8. Control Register Access (CRA) Avalon-MM Slave Port
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5.4. PCI Express Capability Structures
The layout of the most basic Capability Structures are provided below. Refer to the PCI Express Base Specification for more information about these registers.
Figure 21. MSI Capability Structure
Figure 22. MSI-X Capability Structure
Figure 23. Power Management Capability Structure - Byte Address Offsets and Layout
Figure 24. PCI Express AER Extended Capability Structure
Note: Refer to the Advanced Error Reporting Capability section for more details about the PCI Express AER Extended Capability Structure.
Figure 25. PCI Express Capability Structure - Byte Address Offsets and LayoutIn the following table showing the PCI Express Capability Structure, registers that are not applicable to a device are reserved.
Note: The Avalon-MM with DMA interface does not support Root Ports.
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