4.3. Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data Rates
In these figures, channels that are not used for the PCI Express protocol are available for other protocols. Unused channels are shown in gray.
For the possible values of <txvr_block_N> and <txvr_block_N+1>, refer to the figures that show the physical location of the Hard IP PCIe blocks in the different types of Intel® Arria® 10 or Intel® Cyclone® 10 GX devices, at the start of this chapter. For each hard IP block, the transceiver block that is adjacent and extends below the hard IP block, is <txvr_block_N>, and the transceiver block that is directly above is <txvr_block_N+1> . For example, in an Intel® Arria® 10 device with 96 transceiver channels and four PCIe hard IP blocks, if your design uses the hard IP block that supports CvP, <txvr_block_N> is GXB1C and <txvr_block_N+1> is GXB1D.
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