Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* Solutions User Guide

ID 683425
Date 6/03/2021
Document Table of Contents

A.2. TLP Packet Formats with Data Payload

Figure 50. Memory Write Request, 32-Bit Addressing
Figure 51. Memory Write Request, 64-Bit Addressing
Figure 52. Configuration Write Request Root Port (Type 1)
Figure 53. I/O Write Request
Figure 54. Completion with Data
Figure 55. Completion Locked with Data
Figure 56. Message with Data