Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* Solutions User Guide

ID 683425
Date 6/03/2021
Public
Document Table of Contents

A.1. TLP Packet Formats without Data Payload

The following figures show the header format for TLPs without a data payload.

Figure 41. Memory Read Request, 32-Bit Addressing
Figure 42. Memory Read Request, Locked 32-Bit Addressing
Figure 43. Memory Read Request, 64-Bit Addressing
Figure 44. Memory Read Request, Locked 64-Bit Addressing
Figure 45. Configuration Read Request Root Port (Type 1)
Figure 46. I/O Read Request
Figure 47. Message without Data

Figure 48. Completion without Data
Figure 49. Completion Locked without Data

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