Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* Solutions User Guide

ID 683425
Date 6/03/2021
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1.8. Resource Utilization

Because the PCIe protocol stack is implemented in hardened logic, it uses no core device resources (no ALMs and no embedded memory).

The Avalon-MM with DMA Intel® Arria® 10 or Intel® Cyclone® 10 GX variants include an Avalon-MM DMA bridge implemented in soft logic that operates as a front end to the hardened protocol stack. The following table shows the typical expected device resource utilization for selected configurations using the current version of the Quartus® Prime software targeting an Intel® Arria® 10 or Intel® Cyclone® 10 GX device. With the exception of M20K memory blocks, the numbers of ALMs and logic registers are rounded up to the nearest 50.

Table 8.  Resource Utilization Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-MM DMA for PCI Express

Data Rate, Number of Lanes, and Interface Width

ALMs

M20K Memory Blocks

Logic Registers

Gen2 x4 128 4300 29 5800

Gen2 x8 128

12700

19

22300

Gen3 x8 256

18000

47

31450