Visible to Intel only — GUID: nik1410564909965
Ixiasoft
1. Datasheet
2. Getting Started with the Avalon-MM DMA
3. Parameter Settings
4. Physical Layout
5. IP Core Interfaces
6. Registers
7. Reset and Clocks
8. Error Handling
9. PCI Express Protocol Stack
10. Arria® 10 or Cyclone® 10 GX Avalon-MM DMA for PCI Express
11. Design Implementation
A. Transaction Layer Packet (TLP) Header Formats
B. Arria® 10 or Cyclone® 10 GX Avalon-MM DMA Interface for PCIe Solutions User Guide Archive
C. Document Revision History
1.1. Arria® 10 or Cyclone® 10 GX Avalon-MM DMA Interface for PCIe* Datasheet
1.2. Features
1.3. Comparison of Avalon-ST, Avalon-MM and Avalon-MM with DMA Interfaces
1.4. Release Information
1.5. Device Family Support
1.6. Design Examples
1.7. IP Core Verification
1.8. Resource Utilization
1.9. Recommended Speed Grades
1.10. Creating a Design for PCI Express
5.1. Arria® 10 or Cyclone® 10 GX DMA Avalon-MM DMA Interface to the Application Layer
5.2. Clock Signals
5.3. Reset, Status, and Link Training Signals
5.4. MSI Interrupts for Endpoints
5.5. Hard IP Reconfiguration Interface
5.6. Physical Layer Interface Signals
5.7. Test Signals
5.8. Arria® 10 Development Kit Conduit Interface
5.1.1. Avalon-MM DMA Interfaces when Descriptor Controller Is Internally Instantiated
5.1.2. Read Data Mover
5.1.3. Write DMA Avalon-MM Master Port
5.1.4. RX Master Module
5.1.5. Non-Bursing Slave Module
5.1.6. 32-Bit Control Register Access (CRA) Slave Signals
5.1.7. Avalon-ST Descriptor Control Interface when Instantiated Separately
5.1.8. Descriptor Controller Interfaces when Instantiated Internally
6.1. Correspondence between Configuration Space Registers and the PCIe Specification
6.2. Type 0 Configuration Space Registers
6.3. Type 1 Configuration Space Registers
6.4. PCI Express Capability Structures
6.5. Intel-Defined VSEC Registers
6.6. Advanced Error Reporting Capability
6.7. DMA Descriptor Controller Registers
6.8. Control Register Access (CRA) Avalon-MM Slave Port
Visible to Intel only — GUID: nik1410564909965
Ixiasoft
6.2. Type 0 Configuration Space Registers
Figure 28. Type 0 Configuration Space Registers - Byte Address Offsets and LayoutEndpoints store configuration data in the Type 0 Configuration Space. The Correspondence between Configuration Space Registers and the PCIe Specification lists the appropriate section of the PCI Express Base Specification that describes these registers.