Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* Solutions User Guide

ID 683425
Date 6/03/2021
Document Table of Contents

8.1. Understanding the Internal DMA Descriptor Controller

When you select Instantiate internal descriptor controller in the parameter editor, the Avalon-MM with DMA includes an internal DMA Descriptor Controller to manage read and write DMA operations. The DMA Descriptor Controller includes read and write data movers to perform local memory reads and writes. It supports up to 128 descriptors for read and write DMAs. Host software programs the DMA Descriptor Controller internal registers with the location and size of the descriptor table residing in the PCI Express main memory. The descriptor control logic directs the DMA read logic to copy the entire table to its local FIFOs.
Figure 37.  Platform Designer Design Example with the Internal DMA Descriptor ControllerThis Platform Designer design example, ep_g3x8_avmm256_integrated.qsys, is available in the <install_dir>/ ip/altera/altera_pcie/altera_pcie_a10_ed/example_design/a10 directory. Refer to Getting Started with the Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-MM DMA for instructions on simulating and compiling this example design. This screen capture filters out some interface types for clarity.
Figure 38. Avalon-MM DMA Block Diagram with the Internal DMA Descriptor ControllerThis block diagram corresponds to the Platform Designer system shown in the previous figure.

This design uses BAR0 and BAR1 to create a 64-bit address to access the DMA Descriptor Controller. These BARs cannot connect to any other interface. If BAR0 must access a different interface, you must use an external DMA descriptor controller. Intel recommends that you select the internal DMA Descriptor Controller if you do not plan to modify this component.

The high-performance BAR2 or BAR2 and BAR3 for 64-bit addresses is available to receive data for other high performance functions.