Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* Solutions User Guide

ID 683425
Date 6/03/2021
Document Table of Contents

The Read Data module sends memory read TLPs. It writes the completion data to an external Avalon-MM interface through the high throughput Read Master port. This data mover operates on descriptors the IP core receives from the DMA Descriptor Controller.

Note: Completion TLPs for the Read Data Mover are restricted to a data payload of up to 256 bytes.

The Read DMA Avalon-MM Master interface performs the following functions:

1. Provides the Descriptor Table to the Descriptor Controller

The Read Data Mover sends PCIe* system memory read requests to fetch the descriptor table from PCIe* system memory. This module then writes the returned descriptor entries in to the Descriptor Controller FIFO using this Avalon-MM interface.

2. Writes Data to Memory Located in Avalon-MM Space

After a DMA Read finishes fetching data from the source address in PCIe* system memory, the Read Data Mover module writes the data to the destination address in Avalon-MM address space via this interface.

Read DMA 256-Bit Avalon-MM Master Interface

Signal Name





When asserted, indicates that the Read DMA module is ready to write read completion data to a memory component in the Avalon-MM address space.



Specifies the write address in the Avalon-MM address space for the read completion data.

RdDmaWriteData_o[127 or 255:0]


The read completion data to be written to the Avalon-MM address space.

RdDmaBurstCount_o[4:0] or [5:0]


Specifies the burst count in 128- or 256-bit words. This bus is 5 bits for the 256-bit interface. It is 6 bits for the 128-bit interface.

RdDmaByteEnable_o[15 or 31:0]


Specifies which DWORDs are valid.



When asserted, indicates that the memory is not ready to receive data.

Read DMA Avalon-MM Master Writes Data to FPGA Memory

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