Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* Solutions User Guide

ID 683425
Date 6/03/2021
Public
Document Table of Contents

3.6. Configuration, Debug, and Extension Options

Table 28.  System Settings for PCI Express

Parameter

Value

Description

Enable configuration via Protocol (CvP)

On/Off

When On, the Quartus® Prime software places the Endpoint in the location required for configuration via protocol (CvP). For more information about CvP, click the Configuration via Protocol (CvP) link below.

CvP is supported for Intel® Cyclone® 10 GX devices from the Intel® Quartus® Prime release 17.1.1 onwards.

Enable dynamic reconfiguration of PCIe read-only registers

On/Off

When On, you can use the Hard IP reconfiguration bus to dynamically reconfigure Hard IP read‑only registers. For more information refer to Hard IP Reconfiguration Interface.

Enable transceiver dynamic reconfiguration On/Off When on, creates an Avalon-MM slave interface that software can drive to update transceiver registers.
Enable Altera Debug Master Endpoint (ADME)

On/Off

When On, an embedded Altera Debug Master Endpoint connects internally to the Avalon-MM slave interface for dynamic reconfiguration. The ADME can access the reconfiguration space of the transceiver. It uses JTAG via the System Console to run tests and debug functions.
Enable Intel® Arria® 10 FPGA Development Kit connection On/Off When On, add control and status conduit interface to the top level variant, to be connected a PCIe Development Kit component.

Did you find the information on this page useful?

Characters remaining:

Feedback Message