Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* Solutions User Guide

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ID 683425
Date 6/03/2021
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Avalon-MM DMA 3. Parameter Settings 4. Physical Layout 5. Registers 6. Error Handling 7. PCI Express Protocol Stack 8. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-MM DMA for PCI Express 9. Design Implementation A. Transaction Layer Packet (TLP) Header Formats B. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-MM DMA Interface for PCIe Solutions User Guide Archive C. Document Revision History
1. Datasheet x
1.1. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-MM DMA Interface for PCIe* Datasheet 1.2. Features 1.3. Comparison of Avalon-ST, Avalon-MM and Avalon-MM with DMA Interfaces 1.4. Release Information 1.5. Device Family Support 1.6. Design Examples 1.7. IP Core Verification 1.8. Resource Utilization 1.9. Recommended Speed Grades 1.10. Creating a Design for PCI Express
1.7. IP Core Verification x
1.7.1. Compatibility Testing Environment
2. Getting Started with the Avalon-MM DMA x
2.1. Understanding the Avalon-MM DMA Ports 2.2. Generating the Testbench 2.3. Simulating the Example Design in ModelSim* 2.4. Running a Gate-Level Simulation 2.5. Generating Synthesis Files 2.6. Compiling the Design 2.7. Creating a Quartus® Prime Project
2.2. Generating the Testbench x
2.2.1. Understanding the Simulation Generated Files 2.2.2. Understanding Simulation Log File Generation
3. Parameter Settings x
3.1. Parameters 3.2. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-MM Settings 3.3. Base Address Register (BAR) Settings 3.4. Device Identification Registers 3.5. PCI Express and PCI Capabilities Parameters 3.6. Configuration, Debug, and Extension Options 3.7. PHY Characteristics 3.8. Example Designs
3.1. Parameters x
3.1.1. RX Buffer Allocation Selections Available by Interface Type
3.5. PCI Express and PCI Capabilities Parameters x
3.5.1. Device Capabilities 3.5.2. Error Reporting 3.5.3. Link Capabilities 3.5.4. MSI and MSI-X Capabilities 3.5.5. Slot Capabilities 3.5.6. Power Management 3.5.7. Vendor Specific Extended Capability (VSEC)
4. Physical Layout x
4.1. Hard IP Block Placement In Intel® Cyclone® 10 GX Devices 4.2. Hard IP Block Placement In Intel® Arria® 10 Devices 4.3. Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data Rates 4.4. Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate 4.5. PCI Express Gen3 Bank Usage Restrictions
5. Registers x
5.1. Correspondence between Configuration Space Registers and the PCIe Specification 5.2. Type 0 Configuration Space Registers 5.3. Type 1 Configuration Space Registers 5.4. PCI Express Capability Structures 5.5. Intel-Defined VSEC Registers 5.6. Advanced Error Reporting Capability 5.7. DMA Descriptor Controller Registers 5.8. Control Register Access (CRA) Avalon-MM Slave Port
5.5. Intel-Defined VSEC Registers x
5.5.1. CvP Registers
5.6. Advanced Error Reporting Capability x
5.6.1. Uncorrectable Internal Error Mask Register 5.6.2. Uncorrectable Internal Error Status Register 5.6.3. Correctable Internal Error Mask Register 5.6.4. Correctable Internal Error Status Register
5.7. DMA Descriptor Controller Registers x
5.7.1. Read DMA Descriptor Controller Registers 5.7.2. Write DMA Descriptor Controller Registers 5.7.3. Read DMA and Write DMA Descriptor Format 5.7.4. Read DMA Example 5.7.5. Software Program for Simultaneous Read and Write DMA
6. Error Handling x
6.1. Physical Layer Errors 6.2. Data Link Layer Errors 6.3. Transaction Layer Errors 6.4. Error Reporting and Data Poisoning 6.5. Uncorrectable and Correctable Error Status Bits
7. PCI Express Protocol Stack x
7.1. Top-Level Interfaces 7.2. Data Link Layer 7.3. Physical Layer
7.1. Top-Level Interfaces x
7.1.1. Avalon-MM DMA Interface 7.1.2. Clocks and Reset 7.1.3. Interrupts 7.1.4. PIPE
8. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-MM DMA for PCI Express x
8.1. Understanding the Internal DMA Descriptor Controller 8.2. Understanding the External DMA Descriptor Controller
9. Design Implementation x
9.1. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 9.2. Recommended Reset Sequence to Avoid Link Training Issues 9.3. SDC Timing Constraints 9.4. Warnings Encountered When Using Narrow Avalon-MM Interfaces
A. Transaction Layer Packet (TLP) Header Formats x
A.1. TLP Packet Formats without Data Payload A.2. TLP Packet Formats with Data Payload
C. Document Revision History x
C.1. Document Revision History for the Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon® Memory Mapped (Avalon-MM) DMA Interface for PCIe* Solutions User Guide
1. Datasheet
2. Getting Started with the Avalon-MM DMA
3. Parameter Settings
4. Physical Layout
5. Registers
6. Error Handling
7. PCI Express Protocol Stack
8. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-MM DMA for PCI Express
9. Design Implementation
A. Transaction Layer Packet (TLP) Header Formats
B. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-MM DMA Interface for PCIe Solutions User Guide Archive
C. Document Revision History

Clock Domains and Clock Generation for the Application LayerThe following illustrates the clock domains when using coreclkout_hip to drive the Application Layer and the pld_clk of the IP core. The Intel-provided example design connects coreclkout_hip to the pld_clk. However, this connection is not mandatory. Inside the Hard IP for PCI Express* , the blocks shown in white are in the pclk domain, while the blocks shown in yellow are in the coreclkout_hip domain.

As this figure indicates, the IP core includes the following clock domains: pclk, coreclkout_hip and pld_clk.


Section Content
coreclkout_hip
pld_clk

Level Two Title