Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* Solutions User Guide

ID 683425
Date 6/03/2021
Document Table of Contents

4.4. Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate

The following figures illustrate the channel placement for the Intel® Arria® 10 Hard IP for PCI Express.

Gen3 variants must initially train at the Gen1 data rate. Consequently, Gen3 variants require an fPLL to generate the 2.5 and 5.0 Gbps clocks, and an ATX PLL to generate the 8.0 Gbps clock. In these figures, channels that are not used for the PCI Express protocol are available for other protocols. Unused channels are shown in gray.

Note: In all configurations, physical channel 4 in the PCS connects to logical channel 0 in the hard IP. You cannot change the channel placements illustrated below.
Figure 15.  Intel® Arria® 10 Gen3 x1 Channel Placement
Figure 16.  Intel® Arria® 10 Gen3 x2 Channel Placement
Figure 17.  Intel® Arria® 10 Gen3 x4 Channel Placement
Figure 18. Gen3 x8 Channel Placement