Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* Solutions User Guide

ID 683425
Date 6/03/2021
Document Table of Contents

This section describes the top-level interfaces in the PCIe variant when it includes the high-performance, burst-capable read data mover and write data mover modules.

Depending on the device, the interface to the Application Layer can be 128 or 256 bits.

Avalon-MM DMA Bridge with Internal Descriptor Controller
Avalon-MM DMA Bridge with External Descriptor Controller

This section describes the interfaces that are required to implement the DMA. All other interfaces are described in the next section, Avalon-MM Interface to the Application Layer.