3.2. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-MM Settings
|Avalon-MM address width||
Specifies the address width for Avalon-MM RX master ports that access Avalon-MM slaves in the Avalon address domain. When you select 32-bit addresses, the PCI Express Avalon-MM DMA bridge performs address translation. When you specify 64-bits addresses, no address translation is performed in either direction. The destination address specified is forwarded to the Avalon-MM interface without any changes.
For the Avalon-MM interface with DMA, this value must be set to 64.
|Enable control register access (CRA) Avalon-MM slave port||On/Off||
Allows read and write access to bridge registers from the interconnect fabric using a specialized slave port. This option is required for Requester/Completer variants and optional for Completer Only variants. Enabling this option allows read and write access to bridge registers, except in the Completer‑Only single dword variations.
|Export MSI/MSI-X conduit interfaces||On/Off||
When you turn this option On, the core exports top‑level MSI and MSI‑X interfaces that you can use to implement a Custom Interrupt Handler for MSI and MSI‑X interrupts. For more information about the Custom Interrupt Handler, refer to Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI‑X Support. If you turn this option Off, the core handles interrupts internally.
|Enable hard IP status bus when using the Avalon-MM interface||On/Off||When you turn this option On, your top-level variant includes signals that are useful for debugging, including link training and status, and error signals. The following signals are included in the top-level variant:
|Instantiate Internal Descriptor Controller||On/Off||When you turn this option On, the descriptor controller is included in the Avalon-MM DMA bridge. When you turn this option off, the descriptor controller should be included as a separate external component. Turn this option on, if you plan to use the Intel-provided descriptor controller in your design. Turn this option off if you plan to modify or replace the descriptor controller logic in your design.|
|Enable burst capabilities for RXM BAR2 port||On/Off||When you turn this option On, the BAR2 RX Avalon-MM masters is burst capable. If BAR2 is 32 bits and Burst capable, then BAR3 is not available for other use. If BAR2 is 64 bits, the BAR3 register holds the upper 32 bits of the address.|
|Enable 256 tags||On/Off||When you turn this option On, the core supports 256 tags, improving the performance of high latency systems. Turning this option on turns on the Extended Tag bit in the Control register.|
|Address width of accessible PCIe memory space||20-64||Specifies the number of bits necessary to access the PCIe address space.|