Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* Solutions User Guide

ID 683425
Date 6/03/2021
Public
Document Table of Contents

9.4. Warnings Encountered When Using Narrow Avalon-MM Interfaces

When the Read and Write Avalon® -MM interfaces used by the Descriptor Controller Slave are 256-bit, but the Read DMA Data Master's Avalon® -MM interface is narrower than 256-bit (for example, this interface is 128-bit in the Gen2x4 configuration), the Intel® Arria® 10 Avalon® -MM DMA PCIe example design creates these two warnings:

Warning: pcie_example_design.DUT.dma_rd_master/DUT.rd_dts_slave: Master DUT.dma_rd_master cannot safely write to slave DUT.rd_dts_slave, because the master data width is narrower than the slave data width. Add byteenable support to the slave to support safe writes from a narrow master.

Warning: pcie_example_design.DUT.dma_rd_master/DUT.wr_dts_slave: Master DUT.dma_rd_master cannot safely write to slave DUT.wr_dts_slave, because the master data width is narrower than the slave data width. Add byteenable support to the slave to support safe writes from a narrow master.

The absence of byte enable support in the DTS interfaces does not cause any functional issue for the 128-bit DMA core. The controller always requests an even number of 128-bit words to the host. When completion data returns, the Platform Designer fabric combines the low and high 128-bit data forming 256 bits of data before sending it to the Descriptor Table Slave (DTS). Therefore, using byte enable masking is not needed for this application. These warnings can be safely ignored.

Did you find the information on this page useful?

Characters remaining:

Feedback Message