Arria® 10 or Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* Solutions User Guide
ID
683425
Date
9/10/2024
Public
1. Datasheet
2. Getting Started with the Avalon-MM DMA
3. Parameter Settings
4. Physical Layout
5. IP Core Interfaces
6. Registers
7. Reset and Clocks
8. Error Handling
9. PCI Express Protocol Stack
10. Arria® 10 or Cyclone® 10 GX Avalon-MM DMA for PCI Express
11. Design Implementation
A. Transaction Layer Packet (TLP) Header Formats
B. Arria® 10 or Cyclone® 10 GX Avalon-MM DMA Interface for PCIe Solutions User Guide Archive
C. Document Revision History
1.1. Arria® 10 or Cyclone® 10 GX Avalon-MM DMA Interface for PCIe* Datasheet
1.2. Features
1.3. Comparison of Avalon-ST, Avalon-MM and Avalon-MM with DMA Interfaces
1.4. Release Information
1.5. Device Family Support
1.6. Design Examples
1.7. IP Core Verification
1.8. Resource Utilization
1.9. Recommended Speed Grades
1.10. Creating a Design for PCI Express
5.1. Arria® 10 or Cyclone® 10 GX DMA Avalon-MM DMA Interface to the Application Layer
5.2. Clock Signals
5.3. Reset, Status, and Link Training Signals
5.4. MSI Interrupts for Endpoints
5.5. Hard IP Reconfiguration Interface
5.6. Physical Layer Interface Signals
5.7. Test Signals
5.8. Arria® 10 Development Kit Conduit Interface
5.1.1. Avalon-MM DMA Interfaces when Descriptor Controller Is Internally Instantiated
5.1.2. Read Data Mover
5.1.3. Write DMA Avalon-MM Master Port
5.1.4. RX Master Module
5.1.5. Non-Bursing Slave Module
5.1.6. 32-Bit Control Register Access (CRA) Slave Signals
5.1.7. Avalon-ST Descriptor Control Interface when Instantiated Separately
5.1.8. Descriptor Controller Interfaces when Instantiated Internally
6.1. Correspondence between Configuration Space Registers and the PCIe Specification
6.2. Type 0 Configuration Space Registers
6.3. Type 1 Configuration Space Registers
6.4. PCI Express Capability Structures
6.5. Intel-Defined VSEC Registers
6.6. Advanced Error Reporting Capability
6.7. DMA Descriptor Controller Registers
6.8. Control Register Access (CRA) Avalon-MM Slave Port
5. IP Core Interfaces
This chapter describes the top-level signals of the Arria® 10 or Cyclone® 10 GX Hard IP for PCI Express* using the Avalon® memory-mapped interface with DMA. The Avalon® memory-mapped interface DMA bridge includes high-performance, burst-capable Read DMA and Write DMA modules. The DMA Descriptor Controller that controls the Read DMA and Write DMA modules can be included in the Avalon® memory-mapped interface DMA bridge or separately instantiated. It uses 64-bit addressing, making address translation unnecessary. A separately instantiated Descriptor Controller manages the Read DMA and Write DMA modules. This variant is available for the following configurations:
- Gen1 x8
- Gen2 x4
- Gen2 x8
- Gen3 x2
- Gen3 x4
- Gen3 x8
Section Content
Arria 10 or Cyclone 10 GX DMA Avalon-MM DMA Interface to the Application Layer
Clock Signals
Reset, Status, and Link Training Signals
MSI Interrupts for Endpoints
Hard IP Reconfiguration Interface
Physical Layer Interface Signals
Test Signals
Arria 10 Development Kit Conduit Interface