Visible to Intel only — GUID: ycf1470379687324
Ixiasoft
Visible to Intel only — GUID: ycf1470379687324
Ixiasoft
6.4.1. Choosing TX PLL Type
Intel® Stratix® 10 and Intel® Arria® 10 Devices
Number of Lanes | 10.3125 G | 12.5 G | 17.4 G | 28 G |
---|---|---|---|---|
1 – 6 | x1 – ATX/fPLL/CMU | x1/x6/xN – ATX/fPLL | x1/x6/xN – ATX | x1/x4 — ATX |
x6/xN – ATX/fPLL | ||||
7 – 24 | x1 – ATX/fPLL/CMU if using multiple PLLs | x1/x6/xN – ATX/fPLL if using 1 or multiple PLLs | x1/x6/xN – ATX if using multiple PLLs (use multiple PLLs as xN with 1.12 V can only support up to 16 G) | Not supported in Serial Lite III Streaming IP core. |
x6/xN – ATX/fPLL if using 1 or multiple PLLs |
Number of Lanes | 10.3125 G | 12.5 G | 17.4 G |
---|---|---|---|
1 – 6 | x1 – ATX/fPLL/CMU | x1/x6/xN – ATX/fPLL | x1/x6/xN – ATX |
x6/xN – ATX/fPLL | |||
7 – 24 | x1 – ATX/fPLL/CMU if using multiple PLLs | x1/x6/xN – ATX/fPLL if using 1 or multiple PLLs | x1/x6/xN – ATX if using multiple PLLs (use multiple PLLs as xN with 1.12 V can only support up to 16 G) |
x6/xN – ATX/fPLL if using 1 or multiple PLLs |
Number of Lanes | 10.3125 G | 12.5 G |
---|---|---|
1 – 6 | x1 – ATX/fPLL/CMU | x1/x6/xN – ATX/fPLL |
x6/xN – ATX/fPLL |
For ATX PLL VCO frequencies between 7.2 GHz and 11.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz), place the ATX PLLs with the gap of seven ATX PLLs apart (skip 6). For ATX PLL VCO frequencies between 11.4 GHz and 14.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz), place the ATX PLLs with the gap of four ATX PLLs apart (skip 3). If these spacing rules are violated, the Intel® Quartus® Prime issues a critical warning. The maximum channel span of a xN clock network is two transceiver banks above and two transceiver banks below the bank that contains the driving PLL and the master CGB. You can use a maximum of 30 channels in a single-bonded or non-bonded xN group. The maximum data rate supported by the xN clock network while driving channels in either the bonded or non-bonded mode depends on the voltage used to drive the transceiver banks and the transceiver speed grade.
Stratix® V and Arria® V Devices
The Serial Lite III Streaming Intel® FPGA IP core in Stratix® V and Arria® V devices allow a selection of PLL type for use inside the transmit and receive PMA blocks. The IP parameter editor in Intel® Quartus® Prime Standard Edition allows you to select either a CMU PLL or an ATX PLL. The CMU PLL is more suitable for lower lane data rates, while the ATX PLL is better for higher lane data rates. The supported data rates for the CMU PLL and ATX PLL are provided in Tables 1 ( Stratix® V) and 2 ( Arria® V GZ). These tables list the maximum lane data rates per transceiver speed grade. For example, if your design requires a 14.1 Gbps lane rate, you need to use an ATX PLL and select a Transceiver Speed Grade 1 device.
Symbol/ Description | Conditions | Transceiver Speed Grade 1 (Mbps) | Transceiver Speed Grade 2 (Mbps) | Transceiver Speed Grade 3 (Mbps) | ||||||
---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | ||
CMU PLL Supported Data Range | _ | 600 | _ | 12500 | 600 | _ | 12500 | 600 | _ | 8500 |
ATX PLL Supported Data Range | VCO Post-divider L=2 |
8000 | _ | 14100 | 8000 | _ | 12500 | 8000 | _ | 8500 |
L=4 | 4000 | _ | 7050 | 4000 | _ | 6600 | 4000 | 6600 | ||
L=8 | 2000 | _ | 3525 | 2000 | _ | 3300 | 2000 | _ | 3300 |
Symbol/ Description | Conditions | Transceiver Speed Grade 2 (Mbps) | Transceiver Speed Grade 3 (Mbps) | ||||
---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | ||
CMU PLL Supported Data Range | _ | 600 | _ | 12500 | 600 | _ | 10312.5 |
ATX PLL Supported Data Range | VCO Post-divider L=2 |
8000 | _ | 12500 | 8000 | _ | 10312.5 |
L=4 | 4000 | _ | 6600 | 4000 | 6600 | ||
L=8 | 2000 | _ | 3300 | 2000 | _ | 3300 |