Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 1/16/2024
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5.1.2.5. Sink Clock Generator

The clock generator is similar to the clock generator in the source core, and is only instantiated in standard clocking mode. The clock generator synthesizes the user clock (user_clock) and core clock (rx_coreclkin) signals from the Native PHY IP core ( Intel® Arria® 10 and Intel® Cyclone® 10 GX devices) or Interlaken PHY IP (Stratix V and Arria V GZ devices) core's output clock signal. The clock generator consists of a fPLL or I/O PLL and a state machine responsible for clock generation and reset sequencing.
Note: For Intel® Stratix® 10 devices, the rx_clkout signal provides the clock for core clock signal (rx_coreclockin) because there is no clock generator module in the IP core.
  • For all Stratix V and Arria V GZ devices, the fPLL generates the user_clock/user_clock_rx and rx_coreclkin based on fixed ratios determined by the IP core's parameter editor.
  • For Intel® Arria® 10 and Intel® Cyclone® 10 GX devices, the I/O PLL generates the user_clock/user_clock_rx based on a fixed ratio, however, the rx_coreclkin operates at the same frequency as rx_clkout.