Serial Lite III Streaming Intel® FPGA IP User Guide

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Date 1/16/2024
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Document Table of Contents
Document Table of Contents x
1. Serial Lite III Streaming Intel® FPGA IP Quick Reference 2. About the Serial Lite III Streaming Intel® FPGA IP 3. Getting Started 4. Serial Lite III Streaming IP Core Design Examples 5. Serial Lite III Streaming Intel® FPGA IP Functional Description 6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines 7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers 8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines 9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives 10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide
2. About the Serial Lite III Streaming Intel® FPGA IP x
2.1. Serial Lite III Streaming Intel® FPGA IP Protocol 2.2. Serial Lite III Streaming Intel® FPGA IP Protocol Operating Modes 2.3. Performance and Resource Utilization
2.2. Serial Lite III Streaming Intel® FPGA IP Protocol Operating Modes x
2.2.1. Continuous Mode 2.2.2. Burst Mode
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Intel® FPGA IP Evaluation Mode 3.3. Specifying IP Core Parameters and Options 3.4. Serial Lite III Streaming Intel® FPGA IP Parameters 3.5. Transceiver Reconfiguration Controller for Stratix® V and Arria® V GZ Designs 3.6. IP Generation Output ( Intel® Quartus® Prime Pro Edition) 3.7. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition) 3.8. Simulating
3.2. Intel® FPGA IP Evaluation Mode x
3.2.1. Intel® FPGA IP Evaluation Mode Timeout Behavior
3.3. Specifying IP Core Parameters and Options x
3.3.1. Serial Lite III Streaming Intel® FPGA IP Parameter Editor 3.3.2. Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs
3.4. Serial Lite III Streaming Intel® FPGA IP Parameters x
3.4.1. Parameters 3.4.2. Parameter Settings for Intel® Stratix® 10 Devices 3.4.3. Parameter Settings for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 3.4.4. Parameter Settings for Stratix V and Arria V GZ Devices
3.8. Simulating x
3.8.1. Simulating Intel® FPGA IP Cores 3.8.2. Simulation Parameters 3.8.3. Simulating and Verifying the Design
4. Serial Lite III Streaming IP Core Design Examples x
4.1. Serial Lite III Streaming IP Core Design Example for Intel® Stratix® 10 Devices 4.2. Serial Lite III Streaming IP Core Design Example for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 4.3. Serial Lite III Streaming IP Design Examples for Stratix® V Devices
5. Serial Lite III Streaming Intel® FPGA IP Functional Description x
5.1. IP Architecture 5.2. Transmission Overheads and Lane Rate Calculations 5.3. Reset 5.4. Link-Up Sequence 5.5. Error Detection, Reporting, and Recovering Mechanism 5.6. CRC-32 Error Injection 5.7. FIFO ECC Protection 5.8. User Data Interface Waveforms 5.9. Signals 5.10. Accessing Configuration and Status Registers
5.1. IP Architecture x
5.1.1. Serial Lite III Streaming Source Core 5.1.2. Serial Lite III Streaming Sink Core 5.1.3. Serial Lite III Streaming IP Core Duplex Core 5.1.4. Interlaken PHY IP Duplex Core or Native PHY IP Duplex Core - Interlaken Mode or PCS Gearbox Mode 5.1.5. Intel® Stratix® 10, Intel® Arria® 10, Intel® Cyclone® 10 GX, Stratix® V, and Arria® V GZ Variations
5.1.1. Serial Lite III Streaming Source Core x
5.1.1.1. Source Application Module 5.1.1.2. Source Adaptation Module 5.1.1.3. Interlaken PHY IP TX Core or Native PHY IP TX Core - Interlaken Mode 5.1.1.4. Source Clock Generator
5.1.2. Serial Lite III Streaming Sink Core x
5.1.2.1. Sink Application Module 5.1.2.2. Sink Adaptation Module 5.1.2.3. Lane Alignment Module 5.1.2.4. Interlaken PHY IP RX Core or Native PHY IP RX Core - Interlaken Mode 5.1.2.5. Sink Clock Generator
5.9. Signals x
5.9.1. Serial Lite III Streaming Intel® FPGA IP Interface Signals 5.9.2. Signals for Intel® Stratix® 10 Devices 5.9.3. Signals for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 5.9.4. Signals for Stratix® V and Arria® V GZ Devices
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines x
6.1. Standard Clocking Mode 6.2. Advanced Clocking Mode 6.3. Standard Clocking Mode vs Advanced Clocking Mode 6.4. Clocking Implementation Guidelines 6.5. Core Latency
6.1. Standard Clocking Mode x
6.1.1. Standard Clocking Mode in Serial Lite III Streaming Intel® FPGA IP Core ( Intel® Stratix® 10 Devices) 6.1.2. Standard Clocking Mode in Intel® Arria® 10, Intel® Cyclone® 10 GX, Stratix® V, and Arria® V Devices
6.2. Advanced Clocking Mode x
6.2.1. Advanced Clocking Mode Structure for Serial Lite III Streaming Intel FPGA IP Core ( Intel® Stratix® 10 Devices) 6.2.2. Advanced Clocking Mode Structure For Intel® Arria® 10, Intel® Cyclone® 10 GX, Stratix® V, and Arria® V Devices
6.4. Clocking Implementation Guidelines x
6.4.1. Choosing TX PLL Type
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers x
7.1. Register Map 7.2. Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines x
8.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy 8.2. Serial Lite III Streaming Intel® FPGA IP Link Debugging
8.2. Serial Lite III Streaming Intel® FPGA IP Link Debugging x
8.2.1. Source Core Link Debugging 8.2.2. Sink Core Link Debugging
1. Serial Lite III Streaming Intel® FPGA IP Quick Reference
2. About the Serial Lite III Streaming Intel® FPGA IP
3. Getting Started
4. Serial Lite III Streaming IP Core Design Examples
5. Serial Lite III Streaming Intel® FPGA IP Functional Description
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines
9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives
10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide

5.9.2. Signals for Intel® Stratix® 10 Devices

Table 24.   Serial Lite III Streaming Source Core Signals for Intel® Stratix® 10 L-tile and H-tile Devices

Signal

Width

Clock Domain

Direction

Description

tx_serial_clk N N/A

Input

This signal is a high-speed serial clock input from the external transceiver PLL. The width is the same as the number of lanes specified in the parameter editor. Each bit of the vector corresponds to serial clock of the transmit channel.

N represents the number of lanes.

tx_pll_locked 1 N/A Input This signal indicates that all external transceiver PLLs are locked. If more than one external transceiver PLL is required for higher lanes, each instantiation outputs a bit that indicates whether the PLL providing the high-speed clock for a corresponding transceiver has achieved its lock status. The pll_locked output signal from the external transceiver PLLs should be ANDed together before being input to the IP core.
xcvr_pll_ref_clk

1

N/A

Input

This signal is the reference clock for the transceivers.
user_clock

1

N/A

Input/Output

Clock for data transfers across the source core interface.

This is an input signal for standard and advanced clocking mode.

user_clock_reset

1

user_clock

Input/Output

Asserts this signal to reset all the user clock domain module.

Available only in Standard Clocking Mode.
link_up

1

user_clock

Output

The core asserts this signal to indicate that the core initialization is complete and is ready to transmit user data.

data

64xN

user_clock

Input

This vector carries the transmitted streaming data to the core.

N represents the number of lanes.

sync

8

 user_clock

Input

The sync vector is an 8 bit bus. The data value at the start of a burst and the end of a burst are captured and transported across the link.

The value at the end of a burst is to indicate the number of invalid 64-bit word in the previous data cycle. As such, for single-lane configuration, the value at the end of a burst is expected to be 0.

Note: This vector is not associated with Interlaken channelization or flow control schemes.
valid

1

user_clock

Input

This single bit signal indicates that the transmitted streaming data is valid.

ready 1 user_clock Output

After a power-on or reset deassertion event, this signal is only asserted after the IP is ready for data transfer, as indicated by tx_link_up. ready deasserts when reset is triggered, tx_link_up deasserted or when the source adaptation FIFO is hitting partial full. This port serves as a status signal to let you know when to backpressure valid_tx.

start_of_burst

1

user_clock

Input

When the core is in burst mode operation, asserting this signal indicates that the information on the data vector is the beginning of a burst.

Because continuous mode is one long burst, in this mode the signal is asserted only once at the start of the data.

end_of_burst

1

user_clock

Input

When the core is in burst mode operation, asserting this signal indicates that the information on the data vector is the end of a burst.

You can optionally send an end of burst signal at the end of continuous mode.

error

4

user_clock

Output

This vector indicates an error or overflow in the source adaptation module’s FIFO buffer.

  • Bit 0: Source adaptation module’s FIFO buffer overflow
  • Bit 1: An SEU error occurred and was corrected (ECC enabled)

    Don't care (ECC disabled)

  • Bit 2: An SEU error occurred and cannot be corrected (ECC enabled)

    Don't care (ECC disabled)

  • Bit 3: A burst gap error occurred due to a mismatch in the BURST GAP parameter value and the gap between end of burst and start of burst.
crc_error_inject 1 user_clock Input This signal forces CRC-32 errors when CRC-32 error injection is enabled in the transceiver channels. The CRC-32 error injection is enabled via the transceiver reconfiguration controller.
err_interrupt 1 phy_mgmt_clk Output

This signal indicates if a transmit error occurs in the current transmission. The signal goes to '1' when any error status bit and its associated interrupt enabled bit have been set to '1'. It goes to '0' after all error status bits with interrupt enabled have been cleared.

Leave unconnected if unused.
Table 25.   Serial Lite III Streaming Sink Core Signals for Intel® Stratix® 10 L-tile and H-tile Devices

Signal

Width

Clock Domain

Direction

Description

xcvr_pll_ref_clk

1

N/A

Input

Reference clock for the transceivers.

user_clock

1

N/A

Output

Clock for data transfers across the sink core interface in the standard clocking mode.

user_clock_reset

1

user_clock

Output

Asserts this signal to reset all the user clock domain module.

Available only in Standard Clocking Mode.
interface_clock

1

core_clock

Output

Clock for data transfer across the sink core interface in the advanced clocking mode.

interface_clock_reset

1

core_clock

Output

The core asserts this signal when the phy_mgmt_clk_reset signal is high and deasserts this signal when the reset sequence is complete in the advanced clocking mode.

Available only in Advanced Clocking Mode.
link_up

1

Standard clocking: user_clock

Advanced clocking: core_clock

Output

The core asserts this signal to indicate that the core initialization is complete and is ready to transmit user data.

When this signal is deasserted, all values in the data_rx signal is invalid regardless of the valid_rx signal value. This means even when the valid_rx signal is asserted, the data_rx signal should be treated as invalid when link_up_rx is deasserted.

data

64xN

Standard clocking: user_clock

Advanced clocking: core_clock

Output

This vector carries the transmitted streaming data from the core.

N represents the number of lanes.

sync

8

Standard clocking: user_clock

Advanced clocking: core_clock

Output

The sync vector is an 8 bit bus that reflects the SYNC value received from the remote partner.

The value at the end of a burst is to indicate the number of invalid 64-bit word in the previous data cycle. As such, for single-lane configuration, the value at the end of a burst is expected to be 0.

Note: This vector is not associated with Interlaken channelization or flow control schemes.
valid

1

Standard clocking: user_clock

Advanced clocking: core_clock

Output

This single bit signal indicates that the data is valid.

start_of_burst

1

Standard clocking: user_clock

Advanced clocking: core_clock

Output

When the core is in burst mode operation, assertion of this signal indicates that the information on the data vector is the beginning of a burst.

Because continuous mode is one long burst, in this mode, the core asserts this signal only once at the start of the data.

end_of_burst

1

Standard clocking: user_clock

Advanced clocking: core_clock

Output

When the core is in burst mode operation, assertion of this signal indicates that the information on the data vector is the end of a burst.

error

N+5

Standard clocking: user_clock

Advanced clocking: core_clock

Output

This vector indicates the state of the sink adaptation module’s FIFO buffer. N represents the number of lanes:

  • [N+4]: An SEU error occurred and cannot be corrected (ECC enabled); Don't care (ECC disabled)

    Don't care (for advanced clocking mode)

  • [N+3]: An SEU error occurred and was corrected (ECC enabled); Don't care (ECC disabled)

    Don't care (for advanced clocking mode)

  • [N+2]: Sink adaptation FIFO overflow

    Don't care (for advanced clocking mode)

  • [N+1]: Don't care. Tied to zero.
  • [N]: Loss of alignment
  • [N-1:0]: PCS sync header, multiframe, or CRC-32 error
ready 1 Standard clocking: user_clock

Advanced clocking: core_clock

Input

This ready signal is for sink IP to check for RX data error. If this signal deasserts during data transfer, it is considered an erroneous condition.

err_interrupt 1 phy_mgmt_clk

Output

This signal indicates if a receive error as occur in the current transmission. The signal goes to '1' when any error status bit and its associated interrupt enabled bit have been set to '1'. It goes to '0' after all error status bits with interrupt enabled have been cleared.

Leave unconnected if unused.
Table 26.   Serial Lite III Streaming Duplex Core Signals for Intel® Stratix® 10 L-tile, H-tile, and E-tile Devices

Signal

Width

Clock Domain

Direction

Description

tx_serial_clk N N/A

Input

This high-speed serial clock input from the external transceiver PLL. The width is the same as the number of lanes specified in the parameter editor. Each bit of the vector corresponds to serial clock of the transmit channel.

N represents the number of lanes.

Note: This signal is not available when you select E-Tile as the transceiver tile.
tx_pll_locked 1 N/A Input This signal indicates that all external transceiver PLLs are locked. If more than one external transceiver PLL is required for higher lanes, each instantiation outputs a bit that indicates whether the PLL providing the high-speed clock for a corresponding transceiver has achieved its lock status. The pll_locked output signal from the external transceiver PLLs should be ANDed together before being input to the IP core.
Note: This signal is not available when you select E-Tile as the transceiver tile.
xcvr_pll_ref_clk

1

N/A

Input

Reference clock for the transceivers.

user_clock_tx

1

N/A

Input

Clock for data transfers across the transmit interface.

user_clock_reset_tx

1

user_clock_tx

Input

In the standard clocking mode, the core asserts this signal when the phy_mgmt_clk_reset signal is high and deasserts this signal when the reset sequence is complete.

In the advanced clocking mode, asserts this signal to reset all user clock domain modules.

interface_clock_reset_tx 1 core_clock Output

In the advanced clocking mode, the core asserts this signal when the phy_mgmt_clk_reset signal is high and deasserts this signal when the reset sequence is complete.

The interface_clock_reset_tx signal asserts when the transceiver PHY is under reset or transceiver PHY's tx_ready is not ready, and deasserts when the transceiver PHY's tx_ready is asserted.

link_up_tx

1

Standard clocking: user_clock

Advanced clocking: core_clock

Output

The core asserts this signal to indicate that the core initialization is complete and is ready to transmit user data.

data_tx

64xN

Standard clocking: user_clock

Advanced clocking: core_clock

Input

This vector carries the transmitted streaming data to the core.

N represents the number of lanes.

sync_tx

8

Standard clocking: user_clock

Advanced clocking: core_clock

Input

The sync vector is an 8 bit bus. The data value at the start of a burst and at the end of a burst are captured and transported across the link.

The value at the end of a burst is to indicate the number of invalid 64-bit word in the previous data cycle. As such, for single-lane configuration, the value at the end of a burst is expected to be 0.

Note: This vector is not associated with Interlaken channelization or flow control schemes.
valid_tx

1

Standard clocking: user_clock

Advanced clocking: core_clock

Input

This vector indicates that the data is valid.

start_of_burst_tx

1

Standard clocking: user_clock

Advanced clocking: core_clock

Input

When the core is in burst mode operation, assertion of this signal indicates that the information on the data vector is the beginning of a burst.

Because continuous mode is one long burst, in this mode the signal is asserted only once at the start of the data.

end_of_burst_tx

1

Standard clocking: user_clock

Advanced clocking: core_clock

Input

When the core is in burst mode operation, assertion of this signal indicates that the information on the data vector is the end of a burst.

error_tx

4

Standard clocking: user_clock

Advanced clocking: core_clock

Output

This vector indicates an overflow in the source adaptation module’s FIFO buffer.

  • Bit 0: Source adaptation module’s FIFO buffer overflow
  • Bit 1: An SEU error occurred and was corrected (ECC enabled).

    Don't care (ECC disabled)

  • Bit 2: An SEU error occurred and cannot be corrected (ECC enabled).

    Don't care (ECC disabled)

  • Bit 3: A burst gap error occurred due to a mismatch in the BURST GAP parameter value and the gap between end of burst and start of burst.
err_interrupt_tx 1 phy_mgmt_clk Output

This signal indicates if a transmit error occurs in the current transmission. The signal goes to '1' when any error status bit and its associated interrupt enabled bit have been set to '1'. It goes to '0' after all error status bits with interrupt enabled have been cleared.

Leave unconnected if unused.
ready_tx 1 user_clock Output

After a power-on or reset deassertion event, this signal is only asserted after the IP is ready for data transfer, as indicated by tx_link_up. ready deasserts when reset is triggered, tx_link_up deasserted or when the source adaptation FIFO is hitting partial full. This port serves as a status signal to let you know when to backpressure valid_tx.

user_clock_rx

1

N/A

Output

Clock for data transfers across the sink core interface in the standard clocking mode.

user_clock_reset_rx

1

user_clock_rx

Output

In the standard clocking mode, the core asserts this signal when the core_reset signal is high and deasserts this signal when the reset sequence is complete.

interface_clock_rx

1

core_clock

Output

Clock for data transfers across the sink core interface in the advanced clocking mode.

interface_clock_reset_rx

1

core_clock

Output

In the advanced clocking mode, the core asserts this signal when the phy_mgmt_clk_reset signal is high and deasserts this signal when the reset sequence is complete.

The interface_clock_reset_rx signal asserts when the transceiver PHY is under reset or transceiver PHY's rx_ready is not ready, and deasserts when the transceiver PHY's rx_ready is asserted.

link_up_rx

1

Standard clocking: user_clock

Advanced clocking: core_clock

Output

The core asserts this signal to indicate that the core initialization is complete and is ready to transmit user data.

When this signal is deasserted, all values in the data_rx signal is invalid regardless of the valid_rx signal value. This means even when the valid_rx signal is asserted, the data_rx signal should be treated as invalid when link_up_rx is deasserted.

data_rx

64xN

Standard clocking: user_clock

Advanced clocking: core_clock

Output

This vector carries the transmitted streaming data from the core.

N represents the number of lanes.

sync_rx

8

Standard clocking: user_clock

Advanced clocking: core_clock

Output

The sync vector is an 8 bit bus that reflects the SYNC value received from the remote partner.

The value at the end of a burst is to indicate the number of invalid 64-bit word in the previous data cycle. As such, for single-lane configuration, the value at the end of a burst is expected to be 0.

Note: This vector is not associated with Interlaken channelization or flow control schemes.
valid_rx

1

Standard clocking: user_clock

Advanced clocking: core_clock

Output

This vector indicates that the data is valid.

start_of_burst_rx

1

Standard clocking: user_clock

Advanced clocking: core_clock

Output

When the core is in burst mode operation, asserting this signal indicates that the information on the data vector is the beginning of a burst.

Because continuous mode is one long burst, in this mode the signal is asserted only once at the start of the data.

end_of_burst_rx

1

Standard clocking: user_clock

Advanced clocking: core_clock

Output

When the core is in burst mode operation, asserting this signal indicates that the information on the data vector is the end of a burst.

You can optionally send an end of burst signal at the end of continuous mode.

error_rx

N+5

Standard clocking: user_clock

Advanced clocking: core_clock

Output

This vector indicates the state of the sink adaptation module’s FIFO buffer. N represents the number of lanes:

  • [N+4]: An SEU error occurred and cannot be corrected (ECC enabled); Don't care (ECC disabled)

    Don't care (for advanced clocking mode)

  • [N+3]: An SEU error occurred and was corrected (ECC enabled); Don't care (ECC disabled)

    Don't care (for advanced clocking mode)

  • [N+2]: Sink adaptation FIFO overflow

    Don't care (for advanced clocking mode)

  • [N+1]: Don't care. Tied to zero.
  • [N]: Loss of alignment
  • [N-1:0]: PCS sync header, multiframe, or CRC-32 error
ready_rx 1 Standard clocking: user_clock

Advanced clocking: core_clock

Input

This ready signal is for sink IP to check for RX data error. If this signal deasserts during data transfer, it is considered an erroneous condition.

err_interrupt_rx 1 phy_mgmt_clk

Output

This signal indicates if a receive error as occur in the current transmission. The signal goes to '1' when any error status bit and its associated interrupt enabled bit have been set to '1'. It goes to '0' after all error status bits with interrupt enabled have been cleared.

Leave unconnected if unused.
crc_error_inject 1 Standard clocking: user_clock_tx

Advanced clocking: core_clock_tx

Input This signal is used for CRC-32 error injection.
Table 27.  L-Tile/H-Tile/E-Tile Transceiver Native PHY Intel® Stratix® 10 IP Core Signals (Interlaken Mode)

Signal

Width

Clock Domain

Direction

Description

phy_mgmt_clk

1

N/A

Input

Clock input for the Avalon memory-mapped PHY management interface within the Native PHY IP core. This signal also clocks the transceiver reconfiguration interface and sequences the reset state machine in the clock generation logic.

Frequency ranges from 100 Hz - 150MHz.
phy_mgmt_clk_reset

1

phy_mgmt_clk

Input

Global reset signal that resets the entire IP including MAC, fPLL (l-tile/H-tile) or I/O PLL (E-tile) (available in standard clocking mode), and Native PHY IP core. This signal is active high and level sensitive.

phy_mgmt_addr

L/H-tile transceiver: 12 + log2N, N=number of lanes

E-tile transceiver: 20 + log2N, N= number of lanes

phy_mgmt_clk

Input

Control and status register (CSR) address for Intel® Stratix® 10 devices.

The width depends on the number of lanes. The parameter editor determines the required width for you. You have to manually tie this extra bit
  • phy_mgmt_addr[msb] = 1: for Transceiver reconfiguration usage
  • phy_mgmt_addr[msb] = 0: for soft CSR (the transceiver reset and loopback control CSR)
phy_mgmt_writedata[31:0]

32

phy_mgmt_clk

Input

CSR write data.

phy_mgmt_readdata[31:0]

32

phy_mgmt_clk

Output

CSR read data.

phy_mgmt_write

1

phy_mgmt_clk

Input

Active high CSR write signal.

phy_mgmt_read

1

phy_mgmt_clk

Input

Active high CSR read signal.

phy_mgmt_waitrequest

1

phy_mgmt_clk

Output

CSR read or write request signal. When asserted, this signal indicates that the Avalon memory-mapped slave interface is unable to respond to a read or write request.

tx_serial_data

N

—

Output

The serial output data from the core.

N represents the number of lanes.

rx_serial_data

N

—

Input

The serial input data to the core.

N represents the number of lanes.

Related Information
6 For more information about this bit, refer to the Interlaken PHY Registers table in the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide and Intel® Stratix® 10 E-Tile Transceiver PHY User Guide.
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