6.2.1. Advanced Clocking Mode Structure for Serial Lite III Streaming Intel FPGA IP Core ( Intel® Stratix® 10 Devices)
In this mode, you must specify the user clock frequency through the Serial Lite III Streaming Intel FPGA IP core parameter editor. Based on the user clock frequency value, the Intel® Quartus® Prime software automatically calculates the lane rate and core clock.
The parameter editor provides guidance in selecting a source user clock frequency that meets the transceiver data rate constraints. For more information about the lane rate calculation, refer to the “Transmission Overheads and Lane Rate Calculations” section.
set_instance_assignment -name GLOBAL_SIGNAL OFF -to *seriallite_iii_streaming*clock_gen:sink_clock_gen|dp_sync:coreclkin_reset_sync|dp_sync_regstage:dp_sync_stage_2*o*
The Serial Lite III Streaming Intel FPGA IP core uses the transmit serial clock bus (tx_serial_clk) and the tx_pll_locked signal to connect the external transmit PLL to the L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP core.
Figure below shows the source and sink variant clocking structure for advanced clocking mode in Intel® Stratix® 10 devices.
|User-defined. This clock is determined by the required throughput of the user application. For example, if the user interface is 384-bits wide (6 lanes × 64 bit/lane) and the required throughput is 120 Gbps, the user_clock frequency is 312.5 MHz. This clock is an input to the IP core and you should toggle this at the specified frequency.
|This clock should toggle at one-half the data rate of the transceiver lane. When you enter the user_clock frequency in the IP parameter editor, the per lane data rate is calculated. Use that value and divided it by two to determine the tx_serial_clk. You are required to instantiate the TX PLL. In the Serial Lite III Streaming design example, an example of the TX PLL (ATX PLL) is generated with the IP core and is configured with the required reference clock and tx_serial_clk.
Note: This signal is not available when you select E-Tile as as the transceiver tile.
|This clock is not exposed to the user. The frequency of tx_clkout is the data rate divided by 64.
|This is an internal clock and it is not exposed to the user. The frequency of this clock is derived from the transceiver data rate. The frequency is lane data rate divided by 64.
|This reference clock is used by the CDR unit in the transceiver. It serves as a reference for the CDR to be able to recover the clock from the serial line. The frequency of this clock must match the frequency you select in the IP parameter editor. It should also match the frequency of the tx_pll_ref_clk reference clock for the TX PLL at the Sink variant for Intel® Stratix® 10 L-tile/H-tile transceiver devices.
|This clock is not exposed to the user. The frequency of rx_clkout is the data rate divided by 64.
|This clock is derived from the transceiver data. It is lane data rate divided by 64. It is an output of the IP core and should be used to clock the RX user application.