Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 1/16/2024
Document Table of Contents Source Clock Generator

When you use standard clocking mode for the user interface, the IP core provides a clock generator to generate the user clock (user_clock) and the Intel® Cyclone® 10 GX and Intel® Arria® 10 Transceiver Native PHY (tx_coreclockin) or Interlaken PHY v18.1 IP (tx_clkout) core clock signals. This clock generator consists of a fPLL ( Stratix® V and Arria® V GZ) or I/O PLL ( Intel® Arria® 10 and Intel® Cyclone® 10 GX) and a state machine responsible for clocks generation and reset sequencing. The user_clock_reset is not released until the fPLL or I/O PLL is locked. The module is used in the standard clocking mode only.
Note: For Intel® Stratix® 10 devices, the tx_clkout signal provides the clock for L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 IP core clock signal (tx_coreclockin) because there is no clock generator module in the Serial Lite III Streaming IP core.
Figure 9. Clock Generator Block Diagram
  • For all Stratix® V and Arria® V GZ devices, the fPLL generates the user_clock/user_clock_tx and tx_coreclkin based on fixed ratios determined by the Serial Lite III Streaming parameter editor.
  • For Intel® Arria® 10 and Intel® Cyclone® 10 GX devices, the I/O PLL generates the user_clock/user_clock_tx based on a fixed ratio, however, the tx_coreclkin operates at the same frequency as tx_clkout.