Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 1/16/2024
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6.5. Core Latency

The table below lists the latency measurement for the Serial Lite III Streaming IP duplex core in standard and advanced clocking mode. An average value is taken from a set of samples during hardware testing. You may see different latency values in simulation.

For a loopback scenario, the core latency measurement is based on the round trip latency from the TX core input to RX core output.

Table 46.   Latency Measurement for Duplex Core
Device Clocking Mode Parameters Latency (ns)
Number of Lanes Per-Lane Data Rate (Mbps)
Intel® Stratix® 10 E-tile Transceiver Standard 4 28,000 260.000
Advanced 4 28,000 241.000
Standard 6 12,500 574.464
Advanced 6 12,500 533.573
Intel® Stratix® 10 L-tile/H-tile Transceiver Standard 4 28,000 8 143.000
Advanced 4 28,0008 117.000
Standard 6 12,500 304.128
Advanced 6 12,500 272.810
Intel® Arria® 10 Standard 5 17,400 174.064
Advanced 5 17,400 154.996
Stratix® V, Arria® V GZ Standard 5 10,312.50 320.964
Advanced 5 10,312.50 292.712
Intel® Cyclone® 10 GX Standard 6 12500 9 247.808
Advanced 6 12500 9 219.498
8 Available only for Intel® Stratix® 10 H-tile transceivers.
9 These latency figures are obtained via simulation (default ECC off) and not with actual hardware.