Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 1/16/2024
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3.8.2. Simulation Parameters

After design generation, simulation files are available for you to simulate your design. To simulate your design, ensure that the Serial Lite III Streaming IP core source and sink cores are both generated with the same parameters or are duplex cores.

  • Stratix V and Arria V GZ files are located in the <variation name>_sim directory
  • Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 files are located in the <variation name> directory

The example testbench simulates the core using the user-specified configuration.

Table 16.  Stratix V and Arria V GZ Testbench Default Simulation Parameters
Parameter Default Value Comments
user clock frequency output (user_clock_frequency) Standard clocking: 145.98375 MHz

Advanced clocking: 146.484375 MHz

Number of lanes (lanes) 2
Transceiver reference clock frequency (pll_ref_freq) 644.53125 MHz
Transceiver data rate (data_rate) 10312.5 Mbps
Meta frame length in words (meta_frame_length) 200
Simulation-specific parameters
Total samples to transfer (total_samples_to_transfer) 2000 Total samples to transfer during simulation.
Mode (mode) Continuous/burst The testbench environment may automatically choose one of the modes depending on the random seed with which it is provided.
Skew insertion enable (skew_insertion_enable) Yes Skew testing is enabled. The testbench environment randomly inserts skew in the lanes within the range 0 - 107 UI.
Enable M20K ECC support (ecc_enable) 0 When set, the core is simulated with the ECC-enabled variant. Use the ECC-enabled variant in the test environment.

When ECC mode is disabled, the two most significant bits of the error buses in the source or sink direction are Don't Care.

Table 17.   Intel® Arria® 10 and Intel® Cyclone® 10 GX Testbench Default Simulation Parameters
Parameter Default Value Comments
user clock frequency output (user_clock_frequency) Standard clocking: 146.484375 MHz
Number of lanes (lanes) 2
Transceiver reference clock frequency (pll_ref_freq) 644.531187 MHz
Transceiver data rate (data_rate) 10.312499 Gbps
Meta frame length in words (meta_frame_length) 200
Simulation-specific parameters
Total samples to transfer (total_samples_to_transfer) 2000 Total samples to transfer during simulation.
Mode (mode) Continuous/burst The testbench environment may automatically choose one of the modes depending on the random seed with which it is provided.
Skew insertion enable (skew_insertion_enable) Yes Skew testing is enabled.

The testbench environment randomly inserts skew in the lanes within the range 0 - 107 UI.

Enable M20K ECC support (ecc_enable) 0 When set, the core is simulated with the ECC-enabled variant. Use the ECC enabled variant in the test environment.

When ECC mode is disabled, the two most significant bits of the error buses in the source or sink direction are Don't Care.

Table 18.   Intel® Stratix® 10 Testbench Default Simulation Parameters
Parameter Default Value Comments
user clock frequency output (user_clock_frequency) Standard clocking: 177.556818 MHz
Number of lanes (lanes) 6
Transceiver reference clock frequency (pll_ref_freq) 312.5 MHz
Transceiver data rate (data_rate) 12.5 Gbps
Meta frame length in words (meta_frame_length) 200
Simulation-specific parameters
Total samples to transfer (total_samples_to_transfer) 2000 Total samples to transfer during simulation.
Mode (mode) Continuous/burst The testbench environment may automatically choose one of the modes depending on the random seed with which it is provided.
Skew insertion enable (skew_insertion_enable) Yes Skew testing is enabled. The testbench environment randomly inserts skew in the lanes within the range 0 - 107 UI.
Enable M20K ECC support (ecc_enable) 0 When set, the core is simulated with the ECC-enabled variant. Use the ECC enabled variant in the test environment.

When ECC mode is disabled, the two most significant bits of the error buses in the source or sink direction are Don't Care.

For more information about Intel FPGA simulation models, refer to the Volume 3 of the Intel® Quartus® Prime Handbook.