Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 1/16/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.1.2. Serial Lite III Streaming Sink Core

The sink core consists of five major functional blocks:

  • L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP and Transceiver Native PHY IP RX core for Intel® Arria® 10 and Intel® Cyclone® 10 GX - Interlaken mode
  • Interlaken PHY v18.1 IP RX core ( Stratix® V or Arria® V GZ devices)
  • Lane alignment module
  • Sink adaptation module (standard clocking mode only)
  • Sink application module
  • Clock generator (in the standard clocking mode for Intel® Arria® 10, Intel® Cyclone® 10 GX, Stratix® V, and Arria® V GZ devices)