Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 1/16/2024
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3.4.3. Parameter Settings for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

Table 13.   IP
Parameter Value Default Description
General Design Options

Direction

Source, Sink, Duplex

Duplex

Supports source, sink, or full duplex transmissions.

Number of lanes

1–24 ( Intel® Arria® 10)

1–6 ( Intel® Cyclone® 10 GX)

2

Specifies the number of lanes (equal to physical transceiver links) that are used to transfer the streaming data.
Transceiver reference clock frequency <Range supported by the transceiver PLLs> 644.53125 MHz Supports multiple transceiver reference clock frequencies for flexibility in the oscillator and PLL choices. This transceiver reference clock frequency must match the external PLL reference clock frequency.

Meta frame length in words

200–8191

200

Specifies the metaframe length.

Enable Transceiver Native PHY ADME On/Off Off Turn on to enable ADME and Optional Reconfiguration Logic parameters of the Transceiver Native PHY IP for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.
Enable M20K ECC support On/Off Off Turn on to use error correcting code (ECC) protection to strengthen the FIFO buffers from single-event upset (SEU) changes. Enables built-in error correcting code (ECC) support on the M20K embedded block memory for single-error correction, double-adjacent-error correction, and triple-adjacent-error detection.
User Interface
Required idle cycles between bursts 1, 2 2 Supports two values to optimize for bandwidth efficiency or maintain backward compatibility with existing Serial Lite III Streaming IP cores (legacy).
  • 1: Recommended for high bandwidth streaming. The same Burst Gap setting must be set for both source and sink IP core.
  • 2: For backward compatibility with Quartus II version 15.1 and older sink IP core.

Clocking mode

Standard clocking mode, Advanced clocking mode

Standard clocking mode

Specifies the clocking mode.

Refer to Serial Lite III Streaming Intel FPGA IP Clocking Guidelines for more information.

User input User clock frequency, Transceiver data rate User clock frequency

Select User clock frequency to specify the user clock input and allow the IP core to determine the transceiver data rate.

Select Transceiver data rate to specify the desired data rate and allow the IP core to determine the user clock frequency.

User clock frequency required

Minimum: 50 MHz

Maximum: Limited by the supported transceiver data rates

150 MHz

Specifies the desired frequency for the user clock input for the transmit (Standard Clocking Mode and Advanced Clocking Mode) and receive user interface (Standard Clocking Mode).

This frequency in turn determines the required transceiver data rate to support the calculated transmit and receive bandwidths.

User clock frequency output

Minimum: 50 MHz

Maximum: Limited by the supported transceiver data rates

150 MHz

Specifies the actual user clock frequency as produced by the fPLL or I/O PLL and is ideally the same as the required clock frequency. In certain very high precision situations where the desired user clock is provided up to higher decimal places, this value can vary slightly due to the fPLL or I/O PLL constraints. Change the required clock frequency to correct the issue if the minute variation is intolerable.

Transceiver data rate

required user clock frequency * overheads * 64

10.312499 Gbps

The effective data rate at the output of the transceivers, incorporating transmission and other overheads.

The parameter editor automatically calculates this value by adding the input data rate with transmission overheads to provide you with a selection of user clock frequency.

Aggregate user bandwidth

number of lanes * required user clock frequency * 64

18.75 Gbps

This value is derived by multiplying the number of lanes and user interface data rate.