Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 1/16/2024
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6.4. Clocking Implementation Guidelines

Synchronous Systems

In this scenario, both the Source User Clock and Sink FIFO read clock frequencies are the same. As shown in the figure below, the FIFO read clock is derived from the same crystal oscillator as the Source User Clock. If the Source User Clock requires a PLL, the Sink User Clock should has a PLL with the same configuration.

Figure 24. Same Source and Sink User Clock Frequencies from Same Crystal Oscillator for Intel® Stratix® 10 L-tile/H-tile Transceiver Devices
Figure 25. Same Source and Sink User Clock Frequencies from Same Crystal Oscillator for Intel® Arria® 10, Intel® Cyclone® 10 GX, Stratix V and Arria V GZ Devices

Asynchronous Systems

In an asynchronous system, the sink FIFO read clock is derived from a different crystal oscillator, but has the same frequency as the Source User Clock. In this scenario, a PPM difference exists between the Source User Clock and the FIFO read clock. The Source input data rate needs to be reduced to avoid overflowing the Sink FIFO buffer due to the PPM differences. One recommended way is to insert empty cycles in the Source input data stream at Source User Data Interface to reduce the data rate. The Source Application and Adaptation modules absorb these empty data cycles, convert them to idle cells, and insert them into link data stream. These cells are automatically removed at the sink interface and converted back into empty cycles on the sink user interface.
Note: You have to take into consideration the PPM difference and insert enough empty cycles to offset the PPM difference for the worst case scenario.
Figure 26. Same Source and Sink User Frequencies with Different Crystal Oscillators for Intel® Stratix® 10 L-tile/H-tile Transceiver Devices
Figure 27. Same Source and Sink User Frequencies, with Different Crystal Oscillators for Intel® Arria® 10, Intel® Cyclone® 10 GX, Stratix V and Arria V GZ DevicesFigure illustrates how two crystal oscillators are used to provide the Source User Clock and the Sink FIFO read clock.