Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 1/16/2024
Public
Document Table of Contents
Give Feedback

8.2.1. Source Core Link Debugging

Figure 28. Source Core Link Debugging Flow Chart
Table 51.  Source Link Debugging Signals ( Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, Arria® V GZ, and Stratix® V devices)

Signal Name

Location

( Intel® Arria® 10, Intel® Cyclone® 10 GX, Arria® V GZ, and Stratix® V)

Location

( Intel® Stratix® 10)

Description

link_up_tx

Top level port

Top level port

The core asserts this signal to indicate that initialization sequence is complete and the core is ready to transmit the data.

tx_pll_locked

Native PHY wrapper port

Top level port

This active high signal indicates that the transceivers are locked to the reference clock.

tx_pcs_ready

Native PHY wrapper port

(Encrypted) Soft PHY port

This active high signal indicates that the reset sequence for the source PCS is complete and is ready to accept data.

tx_sync_done

Native PHY wrapper port

PHY top port

This active high signal indicates that all the lanes are bonded by the Native PHY or Interlaken PHY IP core. This signal should be properly asserted for normal operation. A rapidly toggling signal indicates that the source FIFO is having either too much or too little data, or the core reset is having issues.

tx_cal_busy

/source/Interlaken_phy_ip_tx/ sv_ilk_inst

(for Stratix V devices only)

_

Source transceiver calibration status. This active high signal can be used for debugging if the reconfiguration controller is actively calibrating during the initialization sequence.