Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 1/16/2024
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6.3. Standard Clocking Mode vs Advanced Clocking Mode

Table below lists the comparison between two clocking modes that the Serial Lite III Streaming Intel FPGA IP core supports.

Table 40.   Clocking Mode Comparisons
Attribute Standard Clocking Mode Advanced Clocking Mode
Intel® Stratix® 10 Intel® Arria® 10, Intel® Cyclone® 10 GX, Stratix® V, and Arria® V GZ Intel® Stratix® 10 Intel® Arria® 10, Intel® Cyclone® 10 GX, Stratix® V, and Arria® V GZ
User clock sourcing

Generated by the user, provided as an input to the Serial Lite III Streaming Intel FPGA IP core.

The user interface clock is generated by the Serial Lite III Streaming Intel FPGA IP core, provided as an output to the user.

For source core, the user interface clock is generated by the user, provided as an input to the Serial Lite III Streaming Intel FPGA IP core. For sink core, the interface clock is generated by the Serial Lite III Streaming Intel FPGA IP core, provided as an output to the user.

This mode is supported to provide backward compatibility when migrating the IP core from previous devices.

For source core, the user interface clock is generated by the user, provided as an input to the Serial Lite III Streaming Intel FPGA IP core. For sink core, the interface clock is generated by the Serial Lite III Streaming Intel FPGA IP core, provided as an output to the user.

PPM differences between user interface clock and PHY core clock Yes

Intel recommends to use the same clock source as the tx_pll_ref_clk for zero clock PPM implementation.

No Yes Yes
fPLL usage
Note: The fPLLs are located in the FPGA core fabric
Not used in either simplex or duplex cores.

Simplex: 1 per Source core and 1 per Sink core per Serial Lite III Streaming Intel FPGA IP core instance.

Duplex: 2 per Serial Lite III Streaming Intel FPGA IP core instance.

(Lane number does not factor in the use of fPLLs. Only the Serial Lite III Streaming Intel FPGA IP core instances are factored in.)

Not used in either simplex or duplex cores. Not used in either simplex or duplex cores.
Transmission overhead 1.1 1.1 Interlaken overheads Interlaken overheads