Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 1/16/2024
Public
Document Table of Contents
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5.1.5. Intel® Stratix® 10, Intel® Arria® 10, Intel® Cyclone® 10 GX, Stratix® V, and Arria® V GZ Variations

The table summarizes the differences between the Serial Lite III Streaming IP cores in Intel® Stratix® 10, Intel® Arria® 10, Intel® Cyclone® 10 GX, Stratix® V, and Arria® V GZ devices.
Table 21.  Differences between Intel® Stratix® 10, Intel® Arria® 10, Intel® Cyclone® 10 GX, Stratix® V, and Arria® V GZ
Implementation Intel® Stratix® 10 Intel® Arria® 10 and Intel® Cyclone® 10 GX Stratix® V/ Arria® V GZ
Internal clock generator for Standard Clocking Mode Not included.

User clock is provided by user.

Use HSSI refclk to drive fPLL to generate the user clock. You must share the HSSI refclk with the L-tile/H-tile transceiver TX PLL refclk to eliminate PPM difference between user clock domain and core clock domain.

Included.

The IP core uses IOPLL to generate the user clock.

Included.

The IP core uses FPLL to generate the user clock.

Control Status Registers (CSR) for MAC Included. Not included.

Only CSR for transceiver is available.

Not included.

Only CSR for transceiver is available.

Interrupts Included. Not included. Not included.
Transceiver transmit PLL Not included Not included. Included.
Transceiver reconfiguration controller Not required. Not required. Required.
PMA width 64 64 40
Hardware Demonstration Design Example Included. Included. Included (for Stratix® V only)

When you create an instance of the IP core, it dynamically generates an example testbench. This testbench has the same configuration as the IP core instance except for the Burst Gap parameter.

For Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 L-tile/H-tile devices, the Native PHY IP core (Interlaken mode) requires an external transmit PLL. Instantiate the external transmit PLLs and then connect the transmit serial clock output to the tx_serial_clk input. The Serial Lite III Streaming IP core uses a transmit serial clock input bus (tx_serial_clk) and tx_pll_locked input to connect the external transmit PLL to the Intel® Arria® 10 Native PHY IP core. Refer to the Intel® Arria® 10 Transceiver PHY User Guide and Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide for more information.