Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 1/16/2024
Document Table of Contents Interlaken PHY IP RX Core or Native PHY IP RX Core - Interlaken Mode

For Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 L-tile and H-tile devices, this block is an instance of the Native PHY IP core configured for Interlaken - RX only operation. The PMA width for Interlaken mode is 64 bits.

For Stratix V and Arria V GZ devices, the Interlaken module is an instance of the Interlaken PHY IP core configured for RX only operation, and is generated by the Intel® Quartus® Prime parameter editor. The core requires a Stratix V/Arria V GZ Transceiver Reconfiguration Controller for transceiver calibration. The reconfiguration interface size is initially equal to the number of transceiver channels that the sink core uses, which is the number of lanes. The PMA width is 40 bits.