Intel® Arria® 10, Intel® Cyclone® 10 GX, Stratix V and Arria V GZ Reset Scheme
Each core has a separate active high reset signal, core_reset, that asynchronously resets all logic in the core.
Each core also includes the Native PHY or Interlaken PHY IP reset signal, phy_mgmt_clk_reset. This reset signal must be on the same clock domain as the clock used to drive the reconfiguration controllers, phy_mgmt_clk. The Native PHY or Interlaken PHY IP core requires the assertion of this reset signal to synchronize with the reconfiguration controller reset signal.
Intel® Stratix® 10 L-tile/H-tile Transceivers Reset Scheme
For Intel® Stratix® 10 L-tile/H-tile transceivers devices, the IP core uses the phy_mgmt_clk_reset signal to reset all the modules in the IP core and user_clock_reset signal to reset the user clock domain modules e.g. transmit and receive FIFO.
- Use 0x4E2 bit 7 and 3 for TX digital reset.
- Use 0x4E2 bit 6 and 2 for TX analog reset.
- Use 0x4E2 bit 5 and 1 for RX digital reset.
- Use 0x4E2 bit 4 and 0 for RX analog reset.
- Writing 1 to CSR address 0x4E2 to indicates the transmitter listens to the NPDME tx_digitalreset register.
- Writing 1 to CSR address 0x4E2 to initiate a TX digital reset.
- Writing 0 to CSR address 0x4E2 to de-assert a TX digital reset.
Intel® Stratix® 10 E-tile Transceivers Reset Scheme
E-Tile transceivers have separate reset procedures for analog reset and digital reset.
You can use the PMA attribute code 0x0001 on the AVMM reconfiguration bus to enable or disable the PMA. Disabling the PMA puts it in reset. Digital reset can be asserted using the digital reset controller in the Native PHY IP.
- Use the same reset signals for both the source and sink user clock domain modules.
- Synchronize the user_clock_reset signals with phy_mgmt_clock_reset signal assertion.
- Use the phy_mgmt_clk_reset signal to reset the configuration and status registers.
- Ensure all clocks are toggling in a correct rate before de-asserting any reset signals.