Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 4/03/2023

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Genlock Controller Intel® FPGA IP 23. Generic Crosspoint Intel® FPGA IP 24. Genlock Signal Router Intel® FPGA IP 25. Guard Bands Intel® FPGA IP 26. Interlacer Intel® FPGA IP 27. Mixer Intel® FPGA IP 28. Pixels in Parallel Converter Intel® FPGA IP 29. Scaler Intel® FPGA IP 30. Stream Cleaner Intel® FPGA IP 31. Switch Intel® FPGA IP 32. Tone Mapping Operator Intel® FPGA IP 33. Test Pattern Generator Intel® FPGA IP 34. Video Frame Buffer Intel® FPGA IP 35. Video Streaming FIFO Intel® FPGA IP 36. Video Timing Generator Intel® FPGA IP 37. Warp Intel® FPGA IP 38. Design Security 39. Document Revision History for Video and Vision Processing Suite User Guide

5.1. Video and Vision Processing IP Control Examples

Consider which control method best suits your application. Configure the IP according to one of the following methods.
Figure 8.  Full variant with no memory-mapped control interface, fixed operationThe figure shows a video pipeline with a video ingress system (for example, HDMI, Displayport, PCIe) and two IPs, the second IP is the Clipper.

In this system, the full variant clipper IP is parameterized to perform a fixed clip of 1080p HD video clipped down to 720p HD video and has no memory-mapped control interface. The clipper parameters always clip to a height and width of 1280x720 pixels. No further control is necessary as information about the incoming video fields is carried in image information control packets (refer to the Intel FPGA streaming video protocol specification). So, if the input resolution changed to 720p, the clipper reads that information from the image information packets and performs no additional clipping.

The figure shows the video protocol packets from the video ingress subsystem. The packets stream into IP1, which doesn’t change the dimensions of the video. It sends the same image information packets and the same number of data packets into the clipper IP.

The figure shows an image information packet with the video field information for a progressive frame of 1920x1080 pixels. Each video packet carries one line of 1920 pixels.

The image information packet from the clipper contains the new field dimensions of 1280x720 and the clipper only outputs 720 video packets, each of 1280 pixels.

Figure 9. Full variant with memory-mapped control interfaceThe figure shows the same system but with a full variant clipper and with a memory-mapped run-time control interface. A processor in the system connects to the clipper via an Avalon memory-mapped interface.

Most systems need to control IPs so that you can apply different amounts of clipping, scaling or mixing. In this system, the full variant of the clipper IP now includes a memory-mapped control interface. The clipper IP includes a register map and the processor can read the clipper's parameter information and set clipping offsets for any clipping style that you want. When the processor writes any changes to clipping requirements, a final write to the COMMIT register (or receiving a commit auxiliary control packet) ensures they apply when the IP receives the next image information packet to mark the start of the next field.

The processor can also read the dimensions of the incoming video and the count of incoming fields if you turn on Debug features.

Intel recommends this method of control, which is the simplest and most flexible.

Figure 10. Lite variants with mandatory memory-mapped control interfaceThe figure shows the system with the lite variant clipper and a memory-mapped control interface. A processor connects to both the video ingress system and the clipper via Avalon memory-mapped interfaces.

In this example, the lite variant clipper IP is parameterized with the mandatory memory-mapped control interface. In lite variant IPs, the processor writes the field’s properties to the clipper’s IMAGE_INFO registers. The streaming interface just contains video data. Otherwise, control operates as for full variant IPs with memory-mapped control. The processor also writes desired clipping dimensions to the clipper’s register map.