Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Genlock Controller Intel® FPGA IP 23. Generic Crosspoint Intel® FPGA IP 24. Genlock Signal Router Intel® FPGA IP 25. Guard Bands Intel® FPGA IP 26. Interlacer Intel® FPGA IP 27. Mixer Intel® FPGA IP 28. Pixels in Parallel Converter Intel® FPGA IP 29. Scaler Intel® FPGA IP 30. Stream Cleaner Intel® FPGA IP 31. Switch Intel® FPGA IP 32. Tone Mapping Operator Intel® FPGA IP 33. Test Pattern Generator Intel® FPGA IP 34. Video Frame Buffer Intel® FPGA IP 35. Video Streaming FIFO Intel® FPGA IP 36. Video Timing Generator Intel® FPGA IP 37. Warp Intel® FPGA IP 38. Design Security 39. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 3D LUT Intel® FPGA IP x
8.1. About the 3D LUT Intel® FPGA IP 8.2. 3D LUT IP Parameters 8.3. 3D LUT IP Block Description 8.4. 3D LUT IP Registers 8.5. 3D LUT IP Software API
8.1. About the 3D LUT Intel® FPGA IP x
8.1.1. 3D LUT IP Features 8.1.2. 3D LUT IP Performance IP and Resource Information
8.3. 3D LUT IP Block Description x
8.3.1. 3D LUT IP Interfaces 8.3.2. 3D LUT IP Latency
9. AXI-Stream Broadcaster Intel® FPGA IP x
9.1. About the AXI-Stream Broadcaster IP 9.2. AXI-Stream Broadcaster IP Parameters 9.3. AXI-Stream Broadcaster IP Interfaces
9.1. About the AXI-Stream Broadcaster IP x
9.1.1. AXI-Stream Broadcaster IP Features 9.1.2. AXI-Stream Broadcaster IP Performance and Resources
10. Chroma Key Intel® FPGA IP x
10.1. About the Chroma Key IP 10.2. Chroma Key IP Parameters 10.3. Chroma Key IP Interfaces 10.4. Chroma Key Replacement 10.5. Chroma Key IP Registers 10.6. Chroma Key IP Software API
10.1. About the Chroma Key IP x
10.1.1. Chroma Key IP Performance and Resources
11. Chroma Resampler Intel® FPGA IP x
11.1. About the Chroma Resampler IP 11.2. Chroma Resampler IP Parameters 11.3. Chroma Resampler IP Functional Description 11.4. Chroma Resampler IP Registers 11.5. Chroma Resampler IP Software API
11.1. About the Chroma Resampler IP x
11.1.1. Chroma Resampler Performance and Resources
11.3. Chroma Resampler IP Functional Description x
11.3.1. Chroma Resampler IP Interfaces
12. Clipper Intel® FPGA IP x
12.1. About the Clipper IP 12.2. Clipper IP Parameters 12.3. Clipper IP Interfaces 12.4. Clipper IP Registers 12.5. Clipper IP Software API
12.1. About the Clipper IP x
12.1.1. Clipper IP Performance and Resources
13. Clocked Video Input Intel® FPGA IP x
13.1. About the Clocked Video Input IP 13.2. Initializing the Clocked Video Input IP 13.3. Clocked Video Input IP Parameters 13.4. Clocked Video Input IP Interfaces 13.5. Clocked Video Input IP Registers 13.6. Clocked Video Input IP Software API
13.1. About the Clocked Video Input IP x
13.1.1. Clocked Video Input IP Features 13.1.2. Clocked Video Input IP Performance and Resources
14. Clocked Video to Full-Raster Converter Intel® FPGA IP x
14.1. About the Clocked Video to Full-Raster Converter IP 14.2. Clocked Video to Full-Raster Converter Parameters 14.3. Clocked Video to Full-Raster Converter Block Description 14.4. Clocked Video Converter to Full-Raster IP Registers
14.1. About the Clocked Video to Full-Raster Converter IP x
14.1.1. Clocked Video to Full-Raster Converter Features 14.1.2. Clocked Video to Full-Raster Converter Performance and Resources
14.3. Clocked Video to Full-Raster Converter Block Description x
14.3.1. Clocked Video to Full-Raster Converter Interfaces
15. Clocked Video Output Intel® FPGA IP x
15.1. About the Clocked Video Output IP 15.2. Clocked Video Output IP Parameters 15.3. Clocked Video Output IP Functional Description 15.4. Clocked Video Output IP Interfaces 15.5. Clocked Video Output IP Registers 15.6. Clocked Video Output IP Software API
15.1. About the Clocked Video Output IP x
15.1.1. Clocked Video Output IP Performance and Resources 15.1.2. Clocked Video Output IP Features
16. Color Space Converter Intel® FPGA IP x
16.1. About the Color Space Converter IP 16.2. Color Space Converter IP Parameters 16.3. Color Space Converter IP Functional Description 16.4. Color Space Converter IP Registers 16.5. Color Space Converter IP Software API
16.1. About the Color Space Converter IP x
16.1.1. Color Space Converter IP Features 16.1.2. Color Space Converter IP Performance and Resources
16.3. Color Space Converter IP Functional Description x
16.3.1. Color Space Converter IP Interfaces
17. Deinterlacer Intel® FPGA IP x
17.1. About the Deinterlacer IP 17.2. Deinterlacer Parameters 17.3. Deinterlacer Interfaces 17.4. Deinterlacer Registers 17.5. Deinterlacer IP Software API
17.1. About the Deinterlacer IP x
17.1.1. Deinterlacer Performance and Resources
18. FIR Filter Intel® FPGA IP x
18.1. About the FIR Filter 18.2. FIR Filter Parameters 18.3. FIR Filter IP Operation 18.4. FIR Filter Interfaces 18.5. FIR Filter Registers 18.6. FIR Filter IP Software API
18.1. About the FIR Filter x
18.1.1. FIR Filter IP Performance and Resources
18.3. FIR Filter IP Operation x
18.3.1. FIR Filter Processing 18.3.2. FIR Filter Precision 18.3.3. FIR Coefficient Specification 18.3.4. FIR Filter Symmetry 18.3.5. Result to Output Data Type Conversion
18.3.4. FIR Filter Symmetry x
18.3.4.1. No Symmetry 18.3.4.2. Horizontal Symmetry 18.3.4.3. Vertical Symmetry 18.3.4.4. Horizontal and Vertical Symmetry 18.3.4.5. Diagonal Symmetry
19. Frame Cleaner Intel® FPGA IP x
19.1. About the Frame Cleaner IP 19.2. Frame Cleaner IP Parameters 19.3. Frame Cleaner IP Functional Description 19.4. Frame Cleaner IP Interfaces 19.5. Frame Cleaner IP Registers 19.6. Frame Cleaner IP Software API
19.1. About the Frame Cleaner IP x
19.1.1. Frame Cleaner IP Performance and Resources
20. Full-Raster to Clocked Video Converter Intel® FPGA IP x
20.1. About the Full-Raster to Clocked Video Converter 20.2. Full Raster to Clocked Video Converter Parameters 20.3. Full-Raster to Clocked Video Converter Block Description 20.4. Full-Raster to Clocked Video Converter Registers
20.1. About the Full-Raster to Clocked Video Converter x
20.1.1. Full-Raster to Clocked Video Converter Features 20.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
20.3. Full-Raster to Clocked Video Converter Block Description x
20.3.1. Full Raster to Clocked Video Converter Interfaces
21. Full-Raster to Streaming Converter Intel® FPGA IP x
21.1. About the Full-Raster to Streaming Converter IP 21.2. Full-Raster to Streaming Converter Parameters 21.3. Full-Raster to Streaming Converter Block Description
21.1. About the Full-Raster to Streaming Converter IP x
21.1.1. Full-Raster to Streaming Converter Features 21.1.2. Full-Raster to Streaming Converter Performance and Resources
21.3. Full-Raster to Streaming Converter Block Description x
21.3.1. Full-Raster to Streaming Converter Interfaces
22. Genlock Controller Intel® FPGA IP x
22.1. About the Genlock Controller IP 22.2. Genlock Controller IP Parameters 22.3. Genlock Controller IP Functional Description 22.4. Using Genlock Controller IP Software 22.5. Genlock Controller IP Registers 22.6. Genlock Controller IP Software API
22.1. About the Genlock Controller IP x
22.1.1. Genlock Controller IP Performance and Resources
22.3. Genlock Controller IP Functional Description x
22.3.1. Genlock Controller IP Interfaces
22.4. Using Genlock Controller IP Software x
22.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N) 22.4.2. Locking to Reference Clock N (from Genlock Controller IP free running) 22.4.3. Setting the VCXO hold over 22.4.4. Restarting the Genlock Controller IP 22.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old) 22.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa) 22.4.7. Disturbing a Reference Clock (a cable pull)
23. Generic Crosspoint Intel® FPGA IP x
23.1. About the Generic Crosspoint IP 23.2. Generic Crosspoint IP Parameters 23.3. Generic Crosspoint IP Interfaces 23.4. Generic Crosspoint IP Registers 23.5. Generic Crosspoint IP Software API
23.1. About the Generic Crosspoint IP x
23.1.1. Generic Crosspoint IP Features 23.1.2. Generic Crosspoint Performance and Resources
24. Genlock Signal Router Intel® FPGA IP x
24.1. About the Genlock Signal Router IP 24.2. Genlock Signal Router IP Parameters 24.3. Genlock Signal Router IP Interfaces 24.4. Genlock Signal Router IP Registers 24.5. Genlock Signal Router IP Software API
24.1. About the Genlock Signal Router IP x
24.1.1. Genlock Signal Router IP Features 24.1.2. Genlock Signal Router IP Performance and Resources
25. Guard Bands Intel® FPGA IP x
25.1. About the Guard Bands IP 25.2. Guard Bands IP Parameters 25.3. Guard Bands IP Interfaces 25.4. Guard Bands IP Registers 25.5. Guard Bands IP Software API
25.1. About the Guard Bands IP x
25.1.1. Guard Bands IP Performance and Resources
26. Interlacer Intel® FPGA IP x
26.1. About the Interlacer IP 26.2. Interlacer IP Parameters 26.3. Interlacer IP Functional Description 26.4. Interlacer IP Registers 26.5. Interlacer IP Software API
26.1. About the Interlacer IP x
26.1.1. Interlacer IP Performance and Resources
26.3. Interlacer IP Functional Description x
26.3.1. Interlacer IP Interfaces
27. Mixer Intel® FPGA IP x
27.1. About the Mixer IP 27.2. Mixer IP Parameters 27.3. Mixer IP Functional Description 27.4. Mixer IP Registers 27.5. Mixer IP Software API
27.1. About the Mixer IP x
27.1.1. Mixer IP Performance and Resources
27.3. Mixer IP Functional Description x
27.3.1. Mixer IP Interfaces
28. Pixels in Parallel Converter Intel® FPGA IP x
28.1. About the Pixels in Parallel Converter IP 28.2. Pixels in Parallel Converter IP Parameters 28.3. Pixels in Parallel Converter Interfaces 28.4. Pixels in Parallel Converter Registers 28.5. Pixels in Parallel Converter IP Software API
28.1. About the Pixels in Parallel Converter IP x
28.1.1. Pixels in Parallel Converter IP Performance and Resources
29. Scaler Intel® FPGA IP x
29.1. About the Scaler 29.2. Scaler IP Parameters 29.3. Scaler IP Functional Description 29.4. Scaler IP Registers 29.5. Scaler IP Software API
29.1. About the Scaler x
29.1.1. Scaler IP Performance and Resources
29.2. Scaler IP Parameters x
29.2.1. Scaler Maximum Resolution
29.3. Scaler IP Functional Description x
29.3.1. Coefficient Selection 29.3.2. Coefficient Quantization 29.3.3. Filter Behavior at Edge Boundaries 29.3.4. Partial Frame Scaling 29.3.5. 422 and 420 Chroma Sampled Data Scaling 29.3.6. Scaler IP Interfaces
29.3.1. Coefficient Selection x
29.3.1.1. Updating Scaler IP Runtime Coefficients
30. Stream Cleaner Intel® FPGA IP x
30.1. About the Stream Cleaner IP 30.2. Stream Cleaner IP Parameters 30.3. Stream Cleaner IP Functional Description
30.1. About the Stream Cleaner IP x
30.1.1. Stream Cleaner IP Performance and Resources
30.3. Stream Cleaner IP Functional Description x
30.3.1. Stream Cleaner IP Interfaces
31. Switch Intel® FPGA IP x
31.1. About the Switch IP 31.2. Switch IP Parameters 31.3. Switch IP Functional Description 31.4. Switch IP Registers 31.5. Switch IP Software API
31.1. About the Switch IP x
31.1.1. Switch IP Performance and Resources
31.3. Switch IP Functional Description x
31.3.1. Switch IP Latency 31.3.2. Switch IP Interfaces
32. Tone Mapping Operator Intel® FPGA IP x
32.1. About the Tone Mapping Operator IP 32.2. TMO IP Parameters 32.3. TMO IP Block Description 32.4. TMO IP Registers 32.5. TMO IP Software API
32.1. About the Tone Mapping Operator IP x
32.1.1. TMO IP Features 32.1.2. TMO IP Performance and Resource Utilization
32.3. TMO IP Block Description x
32.3.1. TMO IP Interfaces 32.3.2. TMO IP Latency
33. Test Pattern Generator Intel® FPGA IP x
33.1. About the Test Pattern Generator IP 33.2. Test Pattern Generator IP Parameters 33.3. Test Pattern Generator IP Functional Description 33.4. Test Pattern Generator IP Registers 33.5. Test Pattern Generator IP Software API
33.1. About the Test Pattern Generator IP x
33.1.1. Test Pattern Generator IP Performance and Resources
33.3. Test Pattern Generator IP Functional Description x
33.3.1. Test Pattern Generator IP Interfaces
34. Video Frame Buffer Intel® FPGA IP x
34.1. About the Video Frame Buffer IP 34.2. Video Frame Buffer IP Parameters 34.3. Video Frame Buffer IP Functional Description 34.4. Video Frame Buffer IP Registers 34.5. Video Frame Buffer IP Software API
34.1. About the Video Frame Buffer IP x
34.1.1. Video Frame Buffer Performance and Resources
34.3. Video Frame Buffer IP Functional Description x
34.3.1. Video Frame Buffer IP Interfaces
35. Video Streaming FIFO Intel® FPGA IP x
35.1. About the Video Streaming FIFO IP 35.2. Video Streaming FIFO IP Parameters 35.3. Video Streaming FIFO IP Interfaces
35.1. About the Video Streaming FIFO IP x
35.1.1. Video Streaming FIFO IP Performance and Resources
36. Video Timing Generator Intel® FPGA IP x
36.1. About the Video Timing Generator IP 36.2. Video Timing Generator IP Parameters 36.3. Video Timing Generator IP Functional Description 36.4. Video Timing Generator IP Interfaces 36.5. Video Timing Generator IP Registers 36.6. Video Timing Generator IP Software API
36.1. About the Video Timing Generator IP x
36.1.1. Video Timing Generator IP Features 36.1.2. Video Timing Generator IP Performance and Resources
37. Warp Intel® FPGA IP x
37.1. About the Warp IP 37.2. Warp IP Parameters 37.3. Warp IP Block Description 37.4. Warp IP Registers 37.5. Warp IP Software API
37.1. About the Warp IP x
37.1.1. Warp IP Features 37.1.2. Warp IP Performance and Resource Utilization
37.3. Warp IP Block Description x
37.3.1. Block Cache Tool 37.3.2. Warp IP Interfaces 37.3.3. Warp IP Latency 37.3.4. External Memory for Warp IP
37.5. Warp IP Software API x
37.5.1. Using Warp IP Software 37.5.2. Warp IP Software Code Examples
38. Design Security x
38.1. Memory Subsystems 38.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. AXI-Stream Broadcaster Intel® FPGA IP
10. Chroma Key Intel® FPGA IP
11. Chroma Resampler Intel® FPGA IP
12. Clipper Intel® FPGA IP
13. Clocked Video Input Intel® FPGA IP
14. Clocked Video to Full-Raster Converter Intel® FPGA IP
15. Clocked Video Output Intel® FPGA IP
16. Color Space Converter Intel® FPGA IP
17. Deinterlacer Intel® FPGA IP
18. FIR Filter Intel® FPGA IP
19. Frame Cleaner Intel® FPGA IP
20. Full-Raster to Clocked Video Converter Intel® FPGA IP
21. Full-Raster to Streaming Converter Intel® FPGA IP
22. Genlock Controller Intel® FPGA IP
23. Generic Crosspoint Intel® FPGA IP
24. Genlock Signal Router Intel® FPGA IP
25. Guard Bands Intel® FPGA IP
26. Interlacer Intel® FPGA IP
27. Mixer Intel® FPGA IP
28. Pixels in Parallel Converter Intel® FPGA IP
29. Scaler Intel® FPGA IP
30. Stream Cleaner Intel® FPGA IP
31. Switch Intel® FPGA IP
32. Tone Mapping Operator Intel® FPGA IP
33. Test Pattern Generator Intel® FPGA IP
34. Video Frame Buffer Intel® FPGA IP
35. Video Streaming FIFO Intel® FPGA IP
36. Video Timing Generator Intel® FPGA IP
37. Warp Intel® FPGA IP
38. Design Security
39. Document Revision History for Video and Vision Processing Suite User Guide

7.5. Protocol Converter IP Registers

Read and write access to the register map is via the Avalon memory-mapped compliant av_mm_control_agent interface. Turn on Memory-mapped control interface, for access to this interface and access to the register map.
Table 12.  Protocol Converter IP Parameterization RegistersIn the software API these register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE or INTEL_VVP_PROTOCOL_CONV as appropriate and with an optional REG suffix
Address Register Access Description
0x0000 VID_PID RO

Read this register to retrieve the protocol converter vendor ID and product ID.

This register always returns 6AF7_023D.

0x0004 VERSION RO

Read this register to retrieve the version information for the Intel Quartus release that Intel uses to build the protocol converter.

0x0008 CONVERSION_MODE RO

A read to this register returns a value that specifies the input and output protocols for this instance of the Protocol Converter IP.

0 = Avalon streaming video to Intel FPGA streaming video Lite

1 = Intel FPGA streaming video Lite to Avalon streaming video

2 = Avalon streaming video to Intel FPGA streaming video Full

3 = Intel FPGA streaming video Full to Avalon streaming video

4 Intel FPGA streaming video Lite to Intel FPGA streaming video Full

5 = Intel FPGA streaming video Full to Intel FPGA streaming video Lite

0x000C DEBUG_ENABLED RO A read to this register returns the value you select for the Enable debug parameter in this instance of the Protocol converter. The host software can read this value to determine which registers you can read
0x0010 to 0x011F - - Unused.
Table 13.  Protocol Converter IP Control and Debug RegistersIn the software API these register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE or INTEL_VVP_PROTOCOL_CONV as appropriate and with an optional REG suffix For more information, refer to Control Packets.
Address Register Access 5 Description
Not Full Full
0x0120 IMG_INFO_WIDTH RW RO

When the input protocol is Intel FPGA streaming video lite, use this register to set the expected width of incoming video fields.

When the input protocol is Intel FPGA streaming video full and you turn on Debug features, this register returns the width that the protocol converter derives from information in the image information packet. This register is unused if the input protocol is Avalon streaming video.

0x0124 IMG_INFO_HEIGHT RW RO

When the input protocol is Intel FPGA streaming video lite, use this register to set the expected height of incoming video fields.

When the input protocol is Intel FPGA streaming video full and you turn on Debug features, this register returns the height that the protocol converter derives from information in the image information packet. This register is unused if the input protocol is Avalon streaming video.

0x0128 IMG_INFO_INTERLACE RW RO

When the input protocol is Intel FPGA streaming video lite, use this register to set the expected interlacing of incoming video fields.

When the input protocol is Intel FPGA streaming video full and you turn on Debug features, this register returns the interlace code that the protocol converter derives from information in the image information packet. This register is unused if the input protocol is Avalon streaming video.

0x012C Reserved - - Reserved.
0x0130 IMG_INFO_COLORSPACE RW RO

When the input protocol is Intel FPGA streaming video lite or Avalon streaming video, use this register to set the expected color space of incoming video fields.

When the input protocol is Intel FPGA streaming video full and you turn on Debug features, this register returns the color space that the protocol converter derives from information in the image information packet.

0x0134 IMG_INFO_SUBSAMPLING RW RO

When the input protocol is Intel FPGA streaming video lite or Avalon streaming video, use this register to set the expected chroma sampling of incoming video fields.

When the input protocol is Intel FPGA streaming video full and you turn on Debug features, this register returns the chroma sampling that the protocol converter derives from information in the image information packet.

0x0138 IMG_INFO_COSITING RW RO

When the input protocol is Intel FPGA streaming video lite or Avalon streaming video, use this register to set the expected co-siting of incoming video fields.

When the input protocol is Intel FPGA streaming video full and you turn on Debug features, this register returns the cositing that the protocol converter derives from information in the image information packet.

0x013C IMG_INFO_FIELD_COUNT - RO When the input protocol is Intel FPGA streaming video full and you turn on Debug features, this register returns the field count that the protocol converter derives from information in the image information packet. Unused if the input protocol is Avalon streaming video or Intel FPGA streaming video lite.
0x0140 STATUS RO The value you read from this register indicates the processing status of the IP.
0x0144 FIELD_COUNT RO Only used if the output protocol is Intel FPGA streaming video full. A read to this register returns the value of the internal field count, which increments after each output field. The IP uses it to populate the field count values in the output image info and end of frame packets.
0x0148 VIP_WIDTH RO If you select Avalon Streaming Video, for Input protocol variant, a read to this register returns the frame width in the most recently received control packet. The width that the IP reports is a literal decode of the information in the control packet. If the data the IP processes is 4:2:0 chroma sampled, the width that the IP reports is half the actual frame or frame width.
0x014C VIP_HEIGHT RO If you select Avalon Streaming Video for Input protocol variant, a read to this register returns the frame height specified in the most recently received control packet.
0x0150 VIP_INTERLACE RO If you select Avalon Streaming Video for Input protocol variant, a read to this register returns the interlace nibble specified in the most recently received control packet.
0x0154 CTRL RW Writes to this register instruct the IP to start processing video frames, or to stop processing at the next frame boundary. Write a 1 to bit[0] of this register to start the IP. Write a 0 to bit[0] to stop at the next frame boundary. If the IP is already at a frame boundary or is between frames when the write to stop occurs, it stops immediately and does not begin the next frame. The value of this register resets to 0, so if the av_mm_control_agent interface is turned on, the IP resets into the stopped state and you must write a 1 to bit[0] to begin processing.
0x0158 FIELD_COUNT_RESET RW Any write to this register resets the value of the internal field count to zero. The value you write is unimportant. Only if the output protocol is Intel FPGA streaming video full.
0x015C Reserved - Reserved.

Register Bit Descriptions

Table 14.  VID_PID
Name Bits Description
Protocol converter vendor and product ID 31:0 This register always returns 6AF7_023D.
  • 15:0 is the product ID and always returns 6AF7_023D
  • 31:16 is the vendor ID and is always going to be 0x6AF7
Table 15.  VERSION
Name Bits Description
Register map version. bit 7:0 Returns 0x01.
QPDS patch revision 15:8 Returns 0x00.
QPDS update revision 23:16 Updated for each release. For 21.4, returns 0x04.
QPDS major revision 31:24 Updated for each release. For 21.4, returns 0x15.
Table 16.  CONVERSION_MODE
Name Bits Description
Conversion mode 31:0

Returns the protocol conversion mode.

0 = Avalon streaming video to Intel FPGA streaming video lite

1 = Intel FPGA streaming video lite to Avalon streaming video

2 = Avalon streaming video to Intel FPGA streaming video full

3 = Intel FPGA streaming video full to Avalon streaming video

4 = Intel FPGA streaming video lite to Intel FPGA streaming video full

5 = Intel FPGA streaming video full to Intel FPGA streaming video lite

Table 17.  DEBUG_ENABLED
Name Bits Description
Debug features parameterization bit 31:0 Returns 1 if you turn on Debug features and 0 otherwise.
Table 18.   IMG_INFO_WIDTH
Name Bits Description
Width bits 15:0

For parameterizations with Intel FPGA streaming video lite input, write to this register to set the expected width of the incoming video fields.

For parameterizations with Intel FPGA streaming video full input and with debug features on, this register returns the width-1 field from the most recently received image information packet and adds 1 to return a value for width.

unused 31:16 Unused.
Table 19.   IMG_INFO_HEIGHT
Name Bits Description
Height bits 15:0

For parameterizations with Intel FPGA streaming video lite input, write to this register to set the expected height of the incoming video fields.

For parameterizations with Intel FPGA streaming video full input and with debug features on, this register reads the height-1 field from the most recently received image information packet and adds 1 to return a value for height.

unused 31:16 Unused.
Table 20.   IMG_INFO_INTERLACE
Name Bits Description
IntlaceNibble bits 3:0

For parameterizations with Intel FPGA streaming video lite input, write to this register to set the expected interlacing of the incoming video fields.

For parameterizations with Intel FPGA streaming video full input and with debug features enabled, this register returns the intlaceNibble field from the most recently received image information packet .

unused 31:4 Unused.
Table 21.  IMG_INFO_COLORSPACE
Name Bits Description
CSP code bits 6:0

For parameterizations with Intel FPGA streaming video lite or Avalon streaming video input, write to this register to set the expected color space of the incoming video fields.

For parameterizations with Intel FPGA streaming video full input and with debug features on, this register returns the 7 bit CSP field from the most recently received image information packet .

unused 31:7  
Table 22.  IMG_INFO_SUBSAMPLING
Name Bits Description
SubSa code bits 1:0

For parameterizations with Intel FPGA streaming video lite or Avalon streaming video input, write to this register to set the expected subsampling of the incoming video fields.

For parameterizations with Intel FPGA streaming video full input and with debug features on, this register returns the SUBSA field from the most recently received image information packet.

unused 31:2 Unused.
Table 23.  IMG_INFO_COSITING
Name Bits Description
Cosite code bits 1:0

For parameterizations with Intel FPGA streaming video lite or Avalon streaming video input, write to this register to set the expected co-siting of the incoming video fields.

For parameterizations with Intel FPGA streaming video full input and with debug features on, this register returns the COSITE field from the most recently received image information packet.

unused 31:2 Unused.
Table 24.   IMG_INFO_FIELD_COUNT
Name Bits Description
Count bits 6:0 For parameterizations with Intel FPGA streaming video full input and with debug features on, this register returns the 7 bit FIELD_COUNT field from the most recently received image information packet.
unused 31:7 Unused.
Table 25.  STATUS
Name Bits Description
Status bit 0

This bit indicates the IP is currently processing a frame. A value of 1 indicates that the IP is busy processing, a value of 0 indicates that it is idle.

When the input uses the Intel FPGA streaming video lite protocol, the interpretation of bit 0 depends on if you turn on Enable low latency mode. If you turn on Enable low latency mode, the IP sets bit 0 to 1 when it receives the first pixel of the frame and sets it to 0 when it receives the number of lines specified in register map (address 0x124). The IP holds bit 0 at 0 while it flushes any additional lines. If you do not turn on Enable low latency mode, the IP sets bit 0 to 1 at the start of the first frame received and it remains high until you reset the IP.

When the input uses the Intel FPGA streaming video full protocol or Avalon streaming video, the end of a frame sequence is clearly marked by the protocol and bit 0 of the status can be deasserted between frames

Pending register updates bit 1 This bit indicates if the IP has fully processed at least one frame since the last reset. A 1 indicates that the IP has processed at least one, a 0 indicates that the IP has processed no frames.
unused 2 This bit indicates if the last frame the IP receives has the expected number of pixels. A 0 indicates that the frame matched the expected width and height. A 1 indicates that the frame had too many or too few pixels according to these settings.
Table 26.  FIELD_COUNT
Name Bits Description
Field count 31:0 Current value of the internal field counter.
Table 27.  VIP_WIDTH
Name Bits Description
VIP width 15:0 Field width specified in the last Avalon streaming video control packet received at the input.
unused 31:16 Unused.
Table 28.  VIP_HEIGHT
Name Bits Description
VIP height 15:0 Field height specified in the last Avalon streaming video control packet received at the input.
unused 31:16 Unused.
Table 29.  VIP_INTERLACE
Name Bits Description
VIP interlace 3:0 Interlace nibble specified in the last Avalon streaming video control packet received at the input.
unused 31:4 Unused.
Table 30.  CTRL
Name Bits Description
Start / stop bit 0 Write 1 to this bit to start the IP, write 0 to stop the IP.
unused 31:1 Unused.
Table 31.  FIELD_COUNT_RESET
Name Bits Description
unused 31:0 Unused.
5

The function of each of these registers and the access permission, varies depending on which protocol you select for the input interface. The registers are read only (RO) if the input interface is Intel FPGA streaming video full, and RW if the input interface is either Intel FPGA streaming video lite or Avalon streaming video. If the registers are RW, they are only readable if you turn on Debug features parameter.

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