31.1. About the Switch IP
The switch supports:
- Up to 8 independent video outputs.
- Up to 8 independent video inputs, configurable to block, consume or drive any number of the 1-8 video outputs.
- Clean or crash switching of video outputs.
- Lite, full, or full raster variants.
- Optional tready signals for full raster variants.
- Clean switching on field boundaries.
- Configurable line switching for lite or full raster variants.
- Propagation of auxiliary control packets with their associated field, for full variants.
- 1 to 8 pixels in parallel and any color space.
- Autoconsume inputs for full variants with clean switching
For more information on lite, full, and full raster variants refer to the Intel FPGA Streaming Video Protocol Specification. The switch IP takes input resolution information from image information packets or from the register interface for lite and full raster variants.
An Avalon memory-mapped interface allows the run-time configuration of the switch.
For information about the reset behavior for the switch, refer to Reset Behavior in Video and Vision IPs Functional Description.
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