Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 4/03/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Genlock Controller Intel® FPGA IP 23. Generic Crosspoint Intel® FPGA IP 24. Genlock Signal Router Intel® FPGA IP 25. Guard Bands Intel® FPGA IP 26. Interlacer Intel® FPGA IP 27. Mixer Intel® FPGA IP 28. Pixels in Parallel Converter Intel® FPGA IP 29. Scaler Intel® FPGA IP 30. Stream Cleaner Intel® FPGA IP 31. Switch Intel® FPGA IP 32. Tone Mapping Operator Intel® FPGA IP 33. Test Pattern Generator Intel® FPGA IP 34. Video Frame Buffer Intel® FPGA IP 35. Video Streaming FIFO Intel® FPGA IP 36. Video Timing Generator Intel® FPGA IP 37. Warp Intel® FPGA IP 38. Design Security 39. Document Revision History for Video and Vision Processing Suite User Guide

31.4. Switch IP Registers

Each register is either read-only (RO) or read-write (RW).

Table 543.  Switch IP RegistersIn the software API the register names appear with a prefix of INTEL_VVP,INTEL_VVP_CORE, or INTEL_VVP_VIDEO SWITCH as appropriate and with an optional REG suffix.
Address Register Access Description
Parameterization registers
0x0000 PROD_ID RO Read this register for the Switch IP product ID. This register always returns 0x0000_0235
0x0004 VERSION RO Read this register for the version information for the Intel Quartus release that Intel uses to build the Switch.
0x0008 INTF_TYPE RO

Read this register to determine the interface type. This register returns:

  • 0 when you select Full interfaces.
  • 1 when you select Lite interfaces.
  • 2 when you select full raster interfaces.
0x000C DEBUG_ENABLED RO Read this register to determine if Debug features are on.
0x0010 UNINTERRUPTED_INPUTS RO Read this register to determine if All inputs are uninterrupted is on.
0x0014 AUTO_CONSUME RO Read this register to determine if Autoconsume is on.
0x0018 NUM_INPUTS RO Read this register to determine the number of configured inputs.
0x001C NUM_OUTPUTS RO Read this register to determine the number of configured outputs.
0x0020 USE_TREADIES RO Read this register to determine if ‘tready’ signal present on switch streaming interfaces is on.
0x0024 CRASH SWITCH RO Read this register to determine if Crash switching is on.
0x0028 to 0x011F RESERVED - Unused.

Control and debug registers

For more details of these registers, refer to Control Packets

0x0120 to 0x13F RESERVED - Unused.
0x0140 STATUS RO

Bit 0: Goes low when a switch starts and returns high when switching completes

Bit 1: Pending run-time control bit. Goes high when a write occurs to one of the input or output control registers. Goes low after a write to the COMMIT register and the IP switch starts the switch.

0x0144 COMMIT RW Write 1 to bit 0 to commit the control register settings and request a new switch. The new switch starts immediately if no switch is currently in progress, otherwise it starts when the current switch completes.
0x0148 INPUT_CONTROL_0 RW 80

Each input has a control register. The IP uses the two input LSBs for control, decoded as follows:

  • 00: disable. Drive TREADY low and do not propagate data.
  • 01: enable. If one of the output registers is configured to receive or consume this input, data propagates, otherwise TREADY is low.
  • 10: disable. Drive TREADY low and do not propagate data.
  • 11: consume. Drive TREADY high but do not propagate data.
0x014C INPUT_CONTROL_1 RW80
0x0150 INPUT_CONTROL_2 RW80
0x0154 INPUT_CONTROL_3 RW80
0x0158 INPUT_CONTROL_4 RW80
0x015C INPUT_CONTROL_5 RW80
0x0160 INPUT_CONTROL_6 RW80
0x0164 INPUT_CONTROL_7 RW80
0x0168 to 0x187 RESERVED - Reserved.
0x0188 OUTPUT_CONTROL_0 RW80

Set bit[8] to enable an output.

Set bits [7:0] to give the integer value of the input to drive the output. An out-of-range input value has the effect of disabling the output.

Inputs and outputs start at zero.

For example, a write of 0x104 to an output control register enables the output and selects input number 4. If the two LSBs in INPUT_CONTROL_4 are 01, the IP enables the connection and input number 4 drives the output.

0x018C OUTPUT_CONTROL_1 RW80
0x0190 OUTPUT_CONTROL_2 RW80
0x0194 OUTPUT_CONTROL_3 RW80
0x0198 OUTPUT_CONTROL_4 RW80
0x019C OUTPUT_CONTROL_5 RW80
0x01A0 OUTPUT_CONTROL_6 RW80
0x01A4 OUTPUT_CONTROL_7 RW80
0x01A8 to 0x01C4 RESERVED - Reserved.

Register Bit Descriptions

Table 544.   PROD_ID
Name Bits Description
Switch product ID 31:0 This register always returns 0x0000_0235
Table 545.  VERSION
Name Bits Description
Register map version 7:0 Register map version. Returns 0x01.
Unused 15:8 Unused. Returns 0x00
QPDS minor revision 23:16 Updated for each release. For 22.4, returns 0x04
QPDS major revision 31:24 Updated for each release. For 22.4, returns 0x16 (22 decimal)
Table 546.   INTF_TYPE
Name Bits Description
Interface type parameterization bits 1:0

A 2-bit interface type register:

  • 00 when you select Full interfaces.
  • 01 when you select Lite interfaces.
  • 10 when you select Full raster interfaces.
  • 11 is illegal and unused.
Unused 31:2 Unused.
Table 547.  DEBUG_ENABLED
Name Bits Description
Debug features 31:0 Unused.
Table 548.   UNINTERRUPTED_INPUTS
Name Bits Description
Uninterrupted inputs parameterization bit 0 Returns 1 if you turn on All inputs are uninterrupted.
Unused 31:1 Unused.
Table 549.   AUTO_CONSUME
Name Bits Description
Autoconsume inputs parameterization bit 0 Returns 1 if you turn on Autoconsume inputs.
Unused 31:1 Unused.
Table 550.   NUM_INPUTS
Name Bits Description
Number of inputs 31:0 Returns the number of inputs configured.
Table 551.   NUM_OUTPUTS
Name Bits Description
Number of outputs 31:0 Returns the number of outputs configured
Table 552.  USE_TREADIES
Name Bits Description
use_ treadies parameterization bit 0 Returns 1 if you turn on ‘tready’ signal present on switch streaming interfaces.
Unused 31:1 Unused.
Table 553.  CRASH_SWITCH
Name Bits Description
Crash switching parameterization bit 0 Returns 1 if you turn on Crash switching.
Unused 31:1 Unused.
Table 554.  STATUS
Name Bits Description
Status bit 0

Goes low when a switch starts and returns high when switching completes

Pending register updates bit 1

Goes high when a write occurs to one of the input or output control registers. Goes low after a write to the COMMIT register and the switch starts.

Unused 31:2 Unused.
Table 555.  COMMIT
Name Bits Description
Commit register 0 Write 1 to commit the control register settings and request a new switch. The new switch starts immediately if no switch is currently in progress, otherwise it starts when the current switch completes.
Unused 31:1 Unused.
Table 556.   INPUT N CONTROL (0 <= N <= 7)
Name Bits Description
Enable bit 0

Enable this input

Consume bit 1 Consume this input. You must enable the input for the consume bit to take effect.
Unused 31:2 Unused.
Table 557.   OUTPUT N CONTROL (0 <= N <= 7)
Name Bits Description
Source 7:0

Integer value of the input source to drive this output. An out-of-range input source value turns off the output.

Enable bit 8

Turn on this output

Unused 31:9 Unused.
80 Read only if you turn on Crash switching.