22.1. About the Genlock Controller IP
You can use the IP in an FPGA to support external voltage-controlled crystal oscillator (VCXO) clock tracking to a reference clock. The IP is highly parameterizable and programmable for various scenarios.
Typically, you generate video receiver and transmitter pixel clocks and video processing clock from three different clock generators. Hence, they are asynchronous. If the video receiver and transmitter clocks are asynchronous, the output video stream drifts over time relative to the input video stream.
The Genlock Controller IP allows locking receiver and transmitter pixel clocks, to avoid any drifting or rolling effect on the output video stream. The video drifting is visually noticeable when the processing video pipeline does not include a frame buffer in it.
The figure shows a video processing pipeline without frame buffer. It shows how adding a genlock to the input and output video affects the output video.
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