Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Genlock Controller Intel® FPGA IP 23. Generic Crosspoint Intel® FPGA IP 24. Genlock Signal Router Intel® FPGA IP 25. Guard Bands Intel® FPGA IP 26. Interlacer Intel® FPGA IP 27. Mixer Intel® FPGA IP 28. Pixels in Parallel Converter Intel® FPGA IP 29. Scaler Intel® FPGA IP 30. Stream Cleaner Intel® FPGA IP 31. Switch Intel® FPGA IP 32. Tone Mapping Operator Intel® FPGA IP 33. Test Pattern Generator Intel® FPGA IP 34. Video Frame Buffer Intel® FPGA IP 35. Video Streaming FIFO Intel® FPGA IP 36. Video Timing Generator Intel® FPGA IP 37. Warp Intel® FPGA IP 38. Design Security 39. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 3D LUT Intel® FPGA IP x
8.1. About the 3D LUT Intel® FPGA IP 8.2. 3D LUT IP Parameters 8.3. 3D LUT IP Block Description 8.4. 3D LUT IP Registers 8.5. 3D LUT IP Software API
8.1. About the 3D LUT Intel® FPGA IP x
8.1.1. 3D LUT IP Features 8.1.2. 3D LUT IP Performance IP and Resource Information
8.3. 3D LUT IP Block Description x
8.3.1. 3D LUT IP Interfaces 8.3.2. 3D LUT IP Latency
9. AXI-Stream Broadcaster Intel® FPGA IP x
9.1. About the AXI-Stream Broadcaster IP 9.2. AXI-Stream Broadcaster IP Parameters 9.3. AXI-Stream Broadcaster IP Interfaces
9.1. About the AXI-Stream Broadcaster IP x
9.1.1. AXI-Stream Broadcaster IP Features 9.1.2. AXI-Stream Broadcaster IP Performance and Resources
10. Chroma Key Intel® FPGA IP x
10.1. About the Chroma Key IP 10.2. Chroma Key IP Parameters 10.3. Chroma Key IP Interfaces 10.4. Chroma Key Replacement 10.5. Chroma Key IP Registers 10.6. Chroma Key IP Software API
10.1. About the Chroma Key IP x
10.1.1. Chroma Key IP Performance and Resources
11. Chroma Resampler Intel® FPGA IP x
11.1. About the Chroma Resampler IP 11.2. Chroma Resampler IP Parameters 11.3. Chroma Resampler IP Functional Description 11.4. Chroma Resampler IP Registers 11.5. Chroma Resampler IP Software API
11.1. About the Chroma Resampler IP x
11.1.1. Chroma Resampler Performance and Resources
11.3. Chroma Resampler IP Functional Description x
11.3.1. Chroma Resampler IP Interfaces
12. Clipper Intel® FPGA IP x
12.1. About the Clipper IP 12.2. Clipper IP Parameters 12.3. Clipper IP Interfaces 12.4. Clipper IP Registers 12.5. Clipper IP Software API
12.1. About the Clipper IP x
12.1.1. Clipper IP Performance and Resources
13. Clocked Video Input Intel® FPGA IP x
13.1. About the Clocked Video Input IP 13.2. Initializing the Clocked Video Input IP 13.3. Clocked Video Input IP Parameters 13.4. Clocked Video Input IP Interfaces 13.5. Clocked Video Input IP Registers 13.6. Clocked Video Input IP Software API
13.1. About the Clocked Video Input IP x
13.1.1. Clocked Video Input IP Features 13.1.2. Clocked Video Input IP Performance and Resources
14. Clocked Video to Full-Raster Converter Intel® FPGA IP x
14.1. About the Clocked Video to Full-Raster Converter IP 14.2. Clocked Video to Full-Raster Converter Parameters 14.3. Clocked Video to Full-Raster Converter Block Description 14.4. Clocked Video Converter to Full-Raster IP Registers
14.1. About the Clocked Video to Full-Raster Converter IP x
14.1.1. Clocked Video to Full-Raster Converter Features 14.1.2. Clocked Video to Full-Raster Converter Performance and Resources
14.3. Clocked Video to Full-Raster Converter Block Description x
14.3.1. Clocked Video to Full-Raster Converter Interfaces
15. Clocked Video Output Intel® FPGA IP x
15.1. About the Clocked Video Output IP 15.2. Clocked Video Output IP Parameters 15.3. Clocked Video Output IP Functional Description 15.4. Clocked Video Output IP Interfaces 15.5. Clocked Video Output IP Registers 15.6. Clocked Video Output IP Software API
15.1. About the Clocked Video Output IP x
15.1.1. Clocked Video Output IP Performance and Resources 15.1.2. Clocked Video Output IP Features
16. Color Space Converter Intel® FPGA IP x
16.1. About the Color Space Converter IP 16.2. Color Space Converter IP Parameters 16.3. Color Space Converter IP Functional Description 16.4. Color Space Converter IP Registers 16.5. Color Space Converter IP Software API
16.1. About the Color Space Converter IP x
16.1.1. Color Space Converter IP Features 16.1.2. Color Space Converter IP Performance and Resources
16.3. Color Space Converter IP Functional Description x
16.3.1. Color Space Converter IP Interfaces
17. Deinterlacer Intel® FPGA IP x
17.1. About the Deinterlacer IP 17.2. Deinterlacer Parameters 17.3. Deinterlacer Interfaces 17.4. Deinterlacer Registers 17.5. Deinterlacer IP Software API
17.1. About the Deinterlacer IP x
17.1.1. Deinterlacer Performance and Resources
18. FIR Filter Intel® FPGA IP x
18.1. About the FIR Filter 18.2. FIR Filter Parameters 18.3. FIR Filter IP Operation 18.4. FIR Filter Interfaces 18.5. FIR Filter Registers 18.6. FIR Filter IP Software API
18.1. About the FIR Filter x
18.1.1. FIR Filter IP Performance and Resources
18.3. FIR Filter IP Operation x
18.3.1. FIR Filter Processing 18.3.2. FIR Filter Precision 18.3.3. FIR Coefficient Specification 18.3.4. FIR Filter Symmetry 18.3.5. Result to Output Data Type Conversion
18.3.4. FIR Filter Symmetry x
18.3.4.1. No Symmetry 18.3.4.2. Horizontal Symmetry 18.3.4.3. Vertical Symmetry 18.3.4.4. Horizontal and Vertical Symmetry 18.3.4.5. Diagonal Symmetry
19. Frame Cleaner Intel® FPGA IP x
19.1. About the Frame Cleaner IP 19.2. Frame Cleaner IP Parameters 19.3. Frame Cleaner IP Functional Description 19.4. Frame Cleaner IP Interfaces 19.5. Frame Cleaner IP Registers 19.6. Frame Cleaner IP Software API
19.1. About the Frame Cleaner IP x
19.1.1. Frame Cleaner IP Performance and Resources
20. Full-Raster to Clocked Video Converter Intel® FPGA IP x
20.1. About the Full-Raster to Clocked Video Converter 20.2. Full Raster to Clocked Video Converter Parameters 20.3. Full-Raster to Clocked Video Converter Block Description 20.4. Full-Raster to Clocked Video Converter Registers
20.1. About the Full-Raster to Clocked Video Converter x
20.1.1. Full-Raster to Clocked Video Converter Features 20.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
20.3. Full-Raster to Clocked Video Converter Block Description x
20.3.1. Full Raster to Clocked Video Converter Interfaces
21. Full-Raster to Streaming Converter Intel® FPGA IP x
21.1. About the Full-Raster to Streaming Converter IP 21.2. Full-Raster to Streaming Converter Parameters 21.3. Full-Raster to Streaming Converter Block Description
21.1. About the Full-Raster to Streaming Converter IP x
21.1.1. Full-Raster to Streaming Converter Features 21.1.2. Full-Raster to Streaming Converter Performance and Resources
21.3. Full-Raster to Streaming Converter Block Description x
21.3.1. Full-Raster to Streaming Converter Interfaces
22. Genlock Controller Intel® FPGA IP x
22.1. About the Genlock Controller IP 22.2. Genlock Controller IP Parameters 22.3. Genlock Controller IP Functional Description 22.4. Using Genlock Controller IP Software 22.5. Genlock Controller IP Registers 22.6. Genlock Controller IP Software API
22.1. About the Genlock Controller IP x
22.1.1. Genlock Controller IP Performance and Resources
22.3. Genlock Controller IP Functional Description x
22.3.1. Genlock Controller IP Interfaces
22.4. Using Genlock Controller IP Software x
22.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N) 22.4.2. Locking to Reference Clock N (from Genlock Controller IP free running) 22.4.3. Setting the VCXO hold over 22.4.4. Restarting the Genlock Controller IP 22.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old) 22.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa) 22.4.7. Disturbing a Reference Clock (a cable pull)
23. Generic Crosspoint Intel® FPGA IP x
23.1. About the Generic Crosspoint IP 23.2. Generic Crosspoint IP Parameters 23.3. Generic Crosspoint IP Interfaces 23.4. Generic Crosspoint IP Registers 23.5. Generic Crosspoint IP Software API
23.1. About the Generic Crosspoint IP x
23.1.1. Generic Crosspoint IP Features 23.1.2. Generic Crosspoint Performance and Resources
24. Genlock Signal Router Intel® FPGA IP x
24.1. About the Genlock Signal Router IP 24.2. Genlock Signal Router IP Parameters 24.3. Genlock Signal Router IP Interfaces 24.4. Genlock Signal Router IP Registers 24.5. Genlock Signal Router IP Software API
24.1. About the Genlock Signal Router IP x
24.1.1. Genlock Signal Router IP Features 24.1.2. Genlock Signal Router IP Performance and Resources
25. Guard Bands Intel® FPGA IP x
25.1. About the Guard Bands IP 25.2. Guard Bands IP Parameters 25.3. Guard Bands IP Interfaces 25.4. Guard Bands IP Registers 25.5. Guard Bands IP Software API
25.1. About the Guard Bands IP x
25.1.1. Guard Bands IP Performance and Resources
26. Interlacer Intel® FPGA IP x
26.1. About the Interlacer IP 26.2. Interlacer IP Parameters 26.3. Interlacer IP Functional Description 26.4. Interlacer IP Registers 26.5. Interlacer IP Software API
26.1. About the Interlacer IP x
26.1.1. Interlacer IP Performance and Resources
26.3. Interlacer IP Functional Description x
26.3.1. Interlacer IP Interfaces
27. Mixer Intel® FPGA IP x
27.1. About the Mixer IP 27.2. Mixer IP Parameters 27.3. Mixer IP Functional Description 27.4. Mixer IP Registers 27.5. Mixer IP Software API
27.1. About the Mixer IP x
27.1.1. Mixer IP Performance and Resources
27.3. Mixer IP Functional Description x
27.3.1. Mixer IP Interfaces
28. Pixels in Parallel Converter Intel® FPGA IP x
28.1. About the Pixels in Parallel Converter IP 28.2. Pixels in Parallel Converter IP Parameters 28.3. Pixels in Parallel Converter Interfaces 28.4. Pixels in Parallel Converter Registers 28.5. Pixels in Parallel Converter IP Software API
28.1. About the Pixels in Parallel Converter IP x
28.1.1. Pixels in Parallel Converter IP Performance and Resources
29. Scaler Intel® FPGA IP x
29.1. About the Scaler 29.2. Scaler IP Parameters 29.3. Scaler IP Functional Description 29.4. Scaler IP Registers 29.5. Scaler IP Software API
29.1. About the Scaler x
29.1.1. Scaler IP Performance and Resources
29.2. Scaler IP Parameters x
29.2.1. Scaler Maximum Resolution
29.3. Scaler IP Functional Description x
29.3.1. Coefficient Selection 29.3.2. Coefficient Quantization 29.3.3. Filter Behavior at Edge Boundaries 29.3.4. Partial Frame Scaling 29.3.5. 422 and 420 Chroma Sampled Data Scaling 29.3.6. Scaler IP Interfaces
29.3.1. Coefficient Selection x
29.3.1.1. Updating Scaler IP Runtime Coefficients
30. Stream Cleaner Intel® FPGA IP x
30.1. About the Stream Cleaner IP 30.2. Stream Cleaner IP Parameters 30.3. Stream Cleaner IP Functional Description
30.1. About the Stream Cleaner IP x
30.1.1. Stream Cleaner IP Performance and Resources
30.3. Stream Cleaner IP Functional Description x
30.3.1. Stream Cleaner IP Interfaces
31. Switch Intel® FPGA IP x
31.1. About the Switch IP 31.2. Switch IP Parameters 31.3. Switch IP Functional Description 31.4. Switch IP Registers 31.5. Switch IP Software API
31.1. About the Switch IP x
31.1.1. Switch IP Performance and Resources
31.3. Switch IP Functional Description x
31.3.1. Switch IP Latency 31.3.2. Switch IP Interfaces
32. Tone Mapping Operator Intel® FPGA IP x
32.1. About the Tone Mapping Operator IP 32.2. TMO IP Parameters 32.3. TMO IP Block Description 32.4. TMO IP Registers 32.5. TMO IP Software API
32.1. About the Tone Mapping Operator IP x
32.1.1. TMO IP Features 32.1.2. TMO IP Performance and Resource Utilization
32.3. TMO IP Block Description x
32.3.1. TMO IP Interfaces 32.3.2. TMO IP Latency
33. Test Pattern Generator Intel® FPGA IP x
33.1. About the Test Pattern Generator IP 33.2. Test Pattern Generator IP Parameters 33.3. Test Pattern Generator IP Functional Description 33.4. Test Pattern Generator IP Registers 33.5. Test Pattern Generator IP Software API
33.1. About the Test Pattern Generator IP x
33.1.1. Test Pattern Generator IP Performance and Resources
33.3. Test Pattern Generator IP Functional Description x
33.3.1. Test Pattern Generator IP Interfaces
34. Video Frame Buffer Intel® FPGA IP x
34.1. About the Video Frame Buffer IP 34.2. Video Frame Buffer IP Parameters 34.3. Video Frame Buffer IP Functional Description 34.4. Video Frame Buffer IP Registers 34.5. Video Frame Buffer IP Software API
34.1. About the Video Frame Buffer IP x
34.1.1. Video Frame Buffer Performance and Resources
34.3. Video Frame Buffer IP Functional Description x
34.3.1. Video Frame Buffer IP Interfaces
35. Video Streaming FIFO Intel® FPGA IP x
35.1. About the Video Streaming FIFO IP 35.2. Video Streaming FIFO IP Parameters 35.3. Video Streaming FIFO IP Interfaces
35.1. About the Video Streaming FIFO IP x
35.1.1. Video Streaming FIFO IP Performance and Resources
36. Video Timing Generator Intel® FPGA IP x
36.1. About the Video Timing Generator IP 36.2. Video Timing Generator IP Parameters 36.3. Video Timing Generator IP Functional Description 36.4. Video Timing Generator IP Interfaces 36.5. Video Timing Generator IP Registers 36.6. Video Timing Generator IP Software API
36.1. About the Video Timing Generator IP x
36.1.1. Video Timing Generator IP Features 36.1.2. Video Timing Generator IP Performance and Resources
37. Warp Intel® FPGA IP x
37.1. About the Warp IP 37.2. Warp IP Parameters 37.3. Warp IP Block Description 37.4. Warp IP Registers 37.5. Warp IP Software API
37.1. About the Warp IP x
37.1.1. Warp IP Features 37.1.2. Warp IP Performance and Resource Utilization
37.3. Warp IP Block Description x
37.3.1. Block Cache Tool 37.3.2. Warp IP Interfaces 37.3.3. Warp IP Latency 37.3.4. External Memory for Warp IP
37.5. Warp IP Software API x
37.5.1. Using Warp IP Software 37.5.2. Warp IP Software Code Examples
38. Design Security x
38.1. Memory Subsystems 38.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. AXI-Stream Broadcaster Intel® FPGA IP
10. Chroma Key Intel® FPGA IP
11. Chroma Resampler Intel® FPGA IP
12. Clipper Intel® FPGA IP
13. Clocked Video Input Intel® FPGA IP
14. Clocked Video to Full-Raster Converter Intel® FPGA IP
15. Clocked Video Output Intel® FPGA IP
16. Color Space Converter Intel® FPGA IP
17. Deinterlacer Intel® FPGA IP
18. FIR Filter Intel® FPGA IP
19. Frame Cleaner Intel® FPGA IP
20. Full-Raster to Clocked Video Converter Intel® FPGA IP
21. Full-Raster to Streaming Converter Intel® FPGA IP
22. Genlock Controller Intel® FPGA IP
23. Generic Crosspoint Intel® FPGA IP
24. Genlock Signal Router Intel® FPGA IP
25. Guard Bands Intel® FPGA IP
26. Interlacer Intel® FPGA IP
27. Mixer Intel® FPGA IP
28. Pixels in Parallel Converter Intel® FPGA IP
29. Scaler Intel® FPGA IP
30. Stream Cleaner Intel® FPGA IP
31. Switch Intel® FPGA IP
32. Tone Mapping Operator Intel® FPGA IP
33. Test Pattern Generator Intel® FPGA IP
34. Video Frame Buffer Intel® FPGA IP
35. Video Streaming FIFO Intel® FPGA IP
36. Video Timing Generator Intel® FPGA IP
37. Warp Intel® FPGA IP
38. Design Security
39. Document Revision History for Video and Vision Processing Suite User Guide

22.5. Genlock Controller IP Registers

The IP allows runtime configuration of parameters via Avalon memory-mapped processor register interface.
Table 357.   Genlock Controller IP Registers
Offset Register Access Description
Parameterization Registers
0x000 VID PID RO

Read this register to retrieve clocked video input product ID. This register always returns 0x6FA7_0170.

0x004 Version number RO Read this register to retrieve the version information for the Intel Quartus release that Intel uses to build this IP.

0x008 to

0x00C

Reserved - Reserved register area.
0x010 CPU clock frequency RO Read this register to retrieve the value for the CPU clock frequency in Hz.
0x014 Number of reference clock RO Read this register to retrieve the value for the number of input reference clocks used by this IP.
0x018 Difference value delta size RO Read this value to retrieve the value for the number of bits this IP uses to calculate the phase or frequency error between two samples.
0x01C Difference value size RO Read this value to retrieve the value for the number of bits this IP uses to calculate the phase or frequency error
0x020 Sample period counter size RO Read this register to retrieve the number of bits this IP uses to generate a sample period counter
0x024 LPF to DAC LSB position RO Read this register to retrieve the position of the LSBs that the IP ignores to calculate the error.
0x028 DAC resolution RO Read this register to retrieve the number of bits this IP uses to set the DAC resolution logic
0x02C PWM Output Clock Divider Value RO Read this register to retrieve the exact value used to divide the clock generating the PWM output pulse
0x030 Derivative enable RO Read this register to check if the derivate logic for this IP is on
0x034 LPF Mode RO Read this register to retrieve the exact mode of operation for the low pass filter
0x038 Proportional gain mode RO Read this register to retrieve the exact mode of operation for the proportional gain
0x03C Integral gain mode RO Read this register to retrieve the exact mode of operation for the integral gain
0x040 Derivative gain mode RO Read this register to retrieve the exact mode of operation for the derivative gain
0x044 VCXO Lock Confidence Counter Size RO Read this register to retrieve the number of bits this IP uses to generate a confidence lock counter
0x048 Enable Debug RO Read this register to check if the debugging logic for this IP is on
Core Specific Registers
0x148 PFD Control RW This register configures the phase and frequency detector logic
0x14C PFD Status RO This register provides debug information about the phase and frequency detector logic
0x150 LPF Control 1 RW This register configures the LPF logic
0x154 LPF Control 2 RW This register configures the LPF logic
0x158 LPF Status RO This register provides debug information about the LPF logic
0x15C DAC Control RW This register configures the DAC control logic
0x160 DAC Status RO This register provides debug information about the DAC control logic
0x164 LPF Control 3 RW This register configures the LPF logic
0x168 Clock Debug Status 1 RO This register provides debug information about the VCXO clock frequency
0x16C Clock Debug Status 2 RO This register provides debug information about the Ref0 clock frequency
0x170 Clock Debug Status 3 RO This register provides debug information about the Ref1 clock frequency
0x174 Clock Debug Status 4 RO This register provides debug information about the Ref2 clock frequency
0x178 Clock Debug Status 5 RO This register provides debug information about the Ref3 clock frequency
0x17C PFD Debug Status RO This register provides debug information about the PFD accumulated error
0x180 to 0x1A0 Reserved - Reserved register area
0x1A4 Tx Rx Ref0 Clock Ratio RW If Ref0 clock frequency is greater than VCXO clock frequency, this register sets the ratio between the two clocks. Otherwise set this register to 1.0
0x1A8 Tx Rx Ref1 Clock Ratio RW If Ref1 clock frequency is greater than VCXO clock frequency, this register sets the ratio between the two clocks. Otherwise set this register to 1.0
0x1AC Tx Rx Ref2 Clock Ratio RW If Ref2 clock frequency is greater than VCXO clock frequency, this register sets the ratio between the two clocks. Otherwise set this register to 1.0
0x1B0 Tx Rx Ref3 Clock Ratio RW If Ref3 clock frequency is greater than VCXO clock frequency, this register sets the ratio between the two clocks. Otherwise set this register to 1.0
0x1B4 Tx Rx VCXO Clock Ratio RW If VCXO clock frequency is greater than reference clock frequency, this register sets the ratio between the two clocks. Otherwise set this register to 1.0

Register Bit Descriptions

Table 358.   PFD Control
Bits Name Description
0 Enable
  • ‘1’ enables the PFD error value e(t) outputs that drive the LPF Inputs.
  • ‘0’ produces no output but the internal counters still run and hence an algorithm restart sequence is required before use. Enable should be the last bit to transition in this register.
3:2 Ref Clock Switch Selection

Determines the reference clock for VCXO tracking:

  • 00=ref0_clk (default)
  • 01=ref1_clk
  • 10=ref2_clk
  • 11=ref3_clk

Clock selection should only select clocks that exist in the design and ideally are running.
7:4 Ref Clock Reset

A 4-bit wide vector where each bit corresponds to an input reference clock (bit 4 = ref0_clk and bit 7 = ref3_clk). A 1 puts that reference places clock counter into reset and out of reset when you write, with bit 12 before you enable the PFD.

12 VCXO Clock Reset

A ‘1’ puts the VCXO clock counter into reset and out of reset when you write ‘0’. Set this bit when you reset the corresponding Ref Clock Reset required for tracking against.

31:16 Output Update Period MSBS

Defines the top 16 MSB of the output update period counter. The LSB are defined by the C_ERR_UPDATE_BITS at build and is the duration of error updates from the PFD to the LPF (and subsequently the DAC).

Set up this value before you use the Enable bit.

Table 359.   PFD Status
Bits Name Description
3:0 Ref Clock Running

A 4 bits vector where each bit corresponds to an input reference clock (bit 0 = ref0_clk and bit 3 = ref3_clk) to indicate that the reference clock appears to be running. Running is based on samples the IP takes against the VCXO clock. If C_ENABLE_DEBUG>0, further clock measure registers are available.

7:4 Ref Clock Stopped

A 4 bits vector where each bit corresponds to an input reference clock (bit 0 = ref0_clk and bit 3 = ref3_clk) to indicate that the reference clock stops changing over the sampling period. These bits are sticky and only reset following an algorithm restart sequence.

If the clock that dies is the current selected reference clock, the PFD does not update any further error changes to the LPF. The IP requires a restart sequence using either another reference clock or the same reference clock if it returns. The output disabled status is indicated in bit 9.

8 Overflow

Indicates an overflow in the difference between the internal tracking counters. An overflow is a serious error and the VCXO can be tracking anywhere. This bit only resets after a restart.

9 Output Disabled

Indicates that the output is currently disabled because of the reference clock dying. The IP makes no further updates to the LPF. This bit only clears following an algorithm restart sequence.

10 diff_diff_value Output Overflow

This output value is smaller than the internal value you use. Indicates an overflow if the smaller value saturates. Consider increasing C_ERR_VAL_BITS. This bit only resets after an algorithm restart.

11 (diff_diff_value – last diff_diff_value) Output Overflow

This output value is smaller than the internal value. Indicates an overflow if the smaller value saturates. Consider increasing C_ERR_VAL_BITS. This bit only resets after a restart.

Table 360.   LPF Control 1
Bits Name Description
0 Enable
  • 1 enables the LPF.
  • 0 keeps it in reset.

You can enable the LPF anytime if the PFD is not enabled as no input values enter the LPF.
1 Integral Accumulator Reset Disable

If the DAC output reaches its maximum value (in either positive or negative direction), it automatically resets the Integral to the reset value as defined in LPF Control 2 register. Writing 1 to this bit stops the automatic reset, which may be useful for debugging.

2 Lock Loss Confidence Count Enable

This bit turns on the confidence counter for detection loss of lock. The IP gains lock when the lock confidence counter reaches its maximum value (C_LOCK_CNT_SIZE) and the IP sees successive no errors. However, a single error causes loss of lock immediately. Enabling this bit allows you to use the same confidence counter for indicating loss of lock. The IP indicates only if it reaches its minimum value of zero loss of. Hence lock status changes only when the extremes of the confidence counter are hit.

7:3 Lock Status LSB Position

By default, the IP allows 1 LSB bit change that does not change the lock status. You can increase the number of LSB bits by up to 31 (to 32 LSB) using these register bits. If the LSB position exceeds the size of the error value (C_CLK_DIV_BITS for diff_val in Phase mode, or C_ERR_VAL_BITS for diff_diff_val in Frequency mode), no amount of error causes the IP to lose lock.

17:16 Locked Status Control

Controls how the IP derives the Locked Status in the LPF Status Register.

00 = Frequency mode. Diff_Diff_Val Input is very small. The IP allows 1 LSB change and still indicates lock. You can increase the LSB position by up to a further 3 positions (to 4) using bits 31:30. Increase when you see larger error values because of larger sampling windows or jittery input.

01 = Phase mode. Diff_Val Input is very small. The IP allows 1 LSB change and still indicates lock. You can increase the LSB position by up to a further 3 positions (to 4) using bits 31:30.

  • 10 = Reserved.
  • 11 = Reserved.
18 I Mode

Defines the integral mode.

  • ‘0’ for Frequency mode where the integral part of the filter performs I = Sum of (I Gain * Diff_Diff_Val)
  • ‘1’ for Phase mode where the integral part of the filter performs I = Sum of (I Gain * Diff_Val)
19 P Mode

Defines the proportional mode

  • ‘0’ for Frequency mode where the proportional part of the filter performs P = P Gain * Diff_Diff_Val
  • ‘1’ for Phase mode where the proportional part of the filter performs P = P Gain * Diff_Val
24 D Mode

Defines the differential mode.

  • ‘0’ for Frequency mode where the differential part of the filter performs D = D Gain * (Diff_Diff_Val – last Diff_Diff_Val)
  • ‘1’ for Phase mode where the differential part of the filter performs D = D Gain * Diff_Diff_Val
25 Negative I Gain

Inverts the sign of the 2’s complement input error. A positive input turns negative and vise-versa for the integral gain. Select this value after selecting I Mode.

26 Negative P Gain

Inverts the sign of the 2’s complement input error A positive input turns negative and vise-versa for the proportional gain. Select this value after selecting P Mode.

27 Negative D Gain

Inverts the sign of the 2’s complement input error. A positive input turns negative and vise-versa for the differential gain. Select this value after selecting D Mode.

28 I Gain Fraction

This bit reverses the direction of the I Gain powers of 2 shift, producing fractions of gain, instead of whole number gain.

29 Reset DAC Saturation Status

Setting high clears any latched DAC Saturation status as indicated in the LPF Status register. You must return this bit low.

Table 361.   LPF Control 2
Bits Name Description
31:0 Integral Accumulator Reset Value

Value the IP loads into the 32 LSBs of the integral accumulator at reset or if it is reset by saturation (if on).

If the internal integral size is greater than 31 bits, the IP uses the MSB of this register as a sign extend.
Table 362.   LPF Status
Bits Name Description
0 Locked

Indicates when the error from the PFD reduces to a very small amount indicating locked status.
1 Integral Overflow

Indicates that an overflow in the integral accumulator is occurring and is reaching its maximum positive or negative value. It remains at that value until reset as part of a restart (refer to Software Usage). This bit indicates a serious error and the VCXO can be tracking anywhere.

2 DAC Saturated

Indicates that the DAC value output from the filter reaches its maximum positive or negative value. It automatically resets the Integral accumulator to its reset value unless you disable it using the LPF Control 1 register bit 1. This bit remains set until you clear it using bit 29 in the LPF Control 1 register.

Table 363.   DAC Control
Bits Name Description
0 Output Enable

‘0’ Outputs High Impedance on the VCXO Driver Pin. ‘1’ enables the DAC to drive the pin. Avoid contention before enabling the DAC and any HW I2C writes in advance.

3:1 DAC Output Data Select

Controls the PWM output via binary offset input value:

  • 000 = sets mid value and VCXO sits at mid frequency
  • 001 = uses value input from LPF Output (converted from 2’s complement, which is just inverted MSB).
  • 010 = sets largest negative value and slowest VCXO frequency
  • 011 = sets largest positive value and fastest VCXO frequency
  • 100 = Use CPU value bits 31:8
  • 101 – 111 = Reserved
4 Hold

Hold value and do not update anymore. Only valid for DAC Output Data Select = 001.

5 Output Force Low

When set, the IP forces the PWM output low and ignores the output mode. Output Force High has a higher priority.

6 Output Force High

When set, the IP forces the PWM output high and ignores the output mode. This bit takes priority over Output Force Low.

7 Output Clock Divide Disable

By default, the IP sets the output clock rate of the DAC control pin using the build time parameter C_DAC_CLK_DIV.

If this bit is 1, the build time divide is disabled, and the output clock rate runs at full speed (which is half the VCXO frequency).

31:8 CPU DAC Output Data Value

Only available if DAC Output Data Select = 100. Value must be offset binary range to the size of the DAC output as in the DAC Status Register. 2’s complement to offset binary conversion is invert MSB.

Examples (assuming 24bit DAC size):

  • 0x000000 sets largest negative value and slowest VCXO frequency
  • 0xFFFFFF sets largest positive value and fastest VCXO frequency
  • 0x800000 sets the mid value and the VCXO sets at its mid frequency
Table 364.   DAC Status
Bits Name Description
23:0 Current DAC Output Data Value

Current offset binary range number that the DAC produces.
Table 365.   LPF Control 3
Bits Name Description
7:0 I Gain

Integral Gain. Provides powers of 2 shifts to the input error value e(t) (2’s complement positive or negative number). The IP adds or subtracts this value into the Integrator before adding it to the final output sum. Valid values are 0 to 15 where 0 means that the IP does not use the integral in the control value to the DAC.

Example: Gain set to 7, gives 2^(7-1) = 64 i.e. the input e(t) is multiplied by 64.

The input error value the IP uses depends on the I Mode bit and is either Diff_Val for Phase Mode or Diff_Diff_Val for Frequency Mode.

You can invert the gain such that in the example above the input can be multiplied by -64. You invert the gain with the Negative I Gain Mode bit.

Modes may not be available because of build parameters even though the bits remain persistent in this control register. Identify build time parameters using the LPF Status register.

15:8 P Gain

Proportional gain. Provides powers of 2 shifts to the input error value e(t) (2’s complement positive or negative number). The IP adds or subtracts this value to the final output sum. Valid values 0 to 15 where 0 means that IP does not use the in the control value to the DAC.

Example: Gain set to 7, gives 2^(7-1) = 64 i.e. the input e(t) is multiplied by 64.

The Input Error Value depends on the P Mode bit and is either Diff_Val for Phase Mode or Diff_Diff_Val for Frequency Mode.

You can invert the gain such that in the example above the input can be multiplied by -64. Set the gain using the Negative P Gain Mode bit.

Additionally, changes the gain shift (left or right) using the I Gain Fraction bit. Right Shifts produce fractional power of 2, which are useful after locking to reduce jitter caused by changes in the input error.

Modes may not be available because of build parameters even though the bits remain persistent in this control register. Use the LPF Status register to identify build time parameters.

23:16 D Gain

Derivative gain. Provides powers of 2 shifts to the input error value e(t) (2’s complement positive or negative number). The IP adds or subtracts this value to the final output sum. Valid values 0 to 15 where 0 means that the derivative is not used in the control value to the DAC.

Example: Gain set to 7, gives 2^(7-1) = 64 i.e. the input e(t) is multiplied by 64.

The input error value depends on the D Mode bit and is either Diff_Diff_Val for Phase Mode or (Diff_Diff_Val – last Diff_Diff_Val) for Frequency Mode.

You can invert the gain such that in the example above the input can be multiplied by -64. Set this gain using the Negative D Gain Mode bit.

Modes may not be available because of build parameters even though the bits remain persistent in this control register. Use the LPF Status register to identify build time parameters.

Table 366.   Clock Debug Status 1
Bits Name Description
31:0 VCXO Clock Measure

Count of clock ticks over 1 second. Zero indicates clock not running. Spurious counts indicate unstable clock. Stable clocks may deviate by a couple of counts because of frequency of CPU clock used to measure against and metastability.

Table 367.   Clock Debug Status 2 to 5
Bits Name Description
31:0 Ref 0-3 Clock Measure

Count of clock ticks over 1 second. Zero indicates clock not running. Spurious counts could indicate unstable clock. Stable clocks may deviate by a couple of counts because of frequency of CPU clock the IP uses to measure against and metastability.

Table 368.   PFD Debug Status
Bits Name Description
31:0 Current e(t)

This value indicates the current internal e(t) value (PFD counter difference value Diff_Val) that represents the continuous error difference value. It is a 2’s complement value representing positive and negative numbers indicating which counter (reference clock or VCXO clock) is ahead.

For Frequency Mode, the error value should trend to a value and remain there. Although it may oscillate around the trend value and drift slowly over time.

For Phase Mode, the error value should reduce to zero and remain there. Although it may oscillate +/- 1. It should not drift over time.

Table 369.   TxRx VCXO Clock Ratio
Bits Name Description
26:22 VCXO Integer number part

Sets the integer part of the clock ratio value. For example, if the clock ratio value is 8.750, this field needs to be set to 8.

21:0 VCXO Fractional number part

Sets the fractional part of the clock ratio value. For example, if the clock ratio value is 8.750, this field needs to be set to (2^22) * (0.750). The 2^22 multiplying factor is because of this IP using 22 bits to represent the fractional part in a fixed-point format.

Table 370.   TxRx Ref 0-3 Clock Ratio
Bits Name Description
26:22 Ref 0-3 Integer number part

Sets the integer part of the clock ratio value. For example, if the clock ratio value is 8.750, this field needs to be set to 8.

21:0 Ref 0-3 Fractional number part

Sets the fractional part of the clock ratio value. For example, if the clock ratio value is 8.750, this field needs to be set to (2^22) * (0.750). The 2^22 multiplying factor is because of this IP using 22 bits to represent the fractional part in a fixed-point format.

Level Two Title