- 22.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N)
- 22.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa)
28.1. About the Pixels in Parallel Converter IP
To help manage data rates, the IP includes the option for a FIFO buffer on the datapath. For conversions that lower the pixels in parallel, the IP locates the FIFO buffer at the input interface, before the conversion logic. For conversions that increase the pixels in parallel, the IP locates the FIFO buffer at the output interface, after the conversion logic. A parameter selects either single clock or dual clock mode for the FIFO buffer. If you select dual clock mode, the input and output interfaces can run on different clock domains.
To correctly implement the pixels in parallel conversion in all cases, the IP must know how many pixels are in each video line. Without this information the IP does not know how many of the pixels in parallel are valid on the final beat of each video line packet. If you configure the IP for use with the full variant of the Intel FPGA streaming video protocol, you can obtain this information directly from the image information packets contained within the video stream. The IP has no requirement for a register map or for the control agent interface to access it. If you configure for the lite variant of the protocol, the video stream has no image information so you must supply the line length through the register map, via the control agent interface. Selecting to use the lite variant of the protocol automatically enables the control agent interface.
Pixels in Parallel Converter IP Performance and Resources
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