1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Genlock Controller Intel® FPGA IP 23. Generic Crosspoint Intel® FPGA IP 24. Genlock Signal Router Intel® FPGA IP 25. Guard Bands Intel® FPGA IP 26. Interlacer Intel® FPGA IP 27. Mixer Intel® FPGA IP 28. Pixels in Parallel Converter Intel® FPGA IP 29. Scaler Intel® FPGA IP 30. Stream Cleaner Intel® FPGA IP 31. Switch Intel® FPGA IP 32. Tone Mapping Operator Intel® FPGA IP 33. Test Pattern Generator Intel® FPGA IP 34. Video Frame Buffer Intel® FPGA IP 35. Video Streaming FIFO Intel® FPGA IP 36. Video Timing Generator Intel® FPGA IP 37. Warp Intel® FPGA IP 38. Design Security 39. Document Revision History for Video and Vision Processing Suite User Guide
22.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N) 22.4.2. Locking to Reference Clock N (from Genlock Controller IP free running) 22.4.3. Setting the VCXO hold over 22.4.4. Restarting the Genlock Controller IP 22.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old) 22.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa) 22.4.7. Disturbing a Reference Clock (a cable pull)
- 22.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N)
- 22.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa)
19.1. About the Frame Cleaner IP
The Intel FPGA Streaming Video protocol allows for the transmission of video fields that do not conform to expected width and height values (field size mismatch errors). The IP removes field size mismatch errors by ensuring that every field matches the expected width and height. The IP either crops or pads errant fields to match the values specified. The IP can use both the full and lite variants of the Intel FPGA Streaming Video protocol.
Every IP in the Video and Vision Processing Suite is tolerant of field size mismatch errors, so including the Frame Cleaner IP in a pipeline built entirely from Intel IPs is not necessary. It can help in the debug processes when building and testing a video pipeline.
If you choose to write your own Intel FPGA streaming video compliant IPs, you may add the Frame Cleaner IP to the pipeline at the input to your IPs. The IP allows you to write the code for your IPs without considering their behavior in all the potential error cases.
Frame Cleaner IP Performance and Resources
Did you find the information on this page useful?