Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 4/03/2023
Public
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Genlock Controller Intel® FPGA IP 23. Generic Crosspoint Intel® FPGA IP 24. Genlock Signal Router Intel® FPGA IP 25. Guard Bands Intel® FPGA IP 26. Interlacer Intel® FPGA IP 27. Mixer Intel® FPGA IP 28. Pixels in Parallel Converter Intel® FPGA IP 29. Scaler Intel® FPGA IP 30. Stream Cleaner Intel® FPGA IP 31. Switch Intel® FPGA IP 32. Tone Mapping Operator Intel® FPGA IP 33. Test Pattern Generator Intel® FPGA IP 34. Video Frame Buffer Intel® FPGA IP 35. Video Streaming FIFO Intel® FPGA IP 36. Video Timing Generator Intel® FPGA IP 37. Warp Intel® FPGA IP 38. Design Security 39. Document Revision History for Video and Vision Processing Suite User Guide

1.5. Glossary of Video and Vision Terminology

Table 3.  Glossary of Video and Vision Terminology
Agent Part of a memory-mapped interface, which receives transactions from a host interface.
Auxiliary control packets A term for any Intel FPGA streaming video protocol control packet with ID>=2. Optionally available to use for a variety of purposes, such as timestamping, register updates, IP synchronization and non-video data such as closed-captioning.
Avalon streaming interface Intel streaming standard, similar to AXI4-Stream. Used by VIP IPs.
Avalon memory-mapped interface Intel memory-mapped interface standard, similar to AXI4-Lite.
Field Either a progressive frame of video, or a field of interlaced video.
Frame A progressive frame of video.
Full variant The variant of the IPs when you turn off Lite mode of the Intel FPGA streaming video protocol and which comprises both control and data packets.
Full-raster variant The variant of the IP of the Intel FPGA streaming video protocol that comprises both blanking and active data packets.
Host Part of a memory-mapped interface, which sends transactions to one or more agent interfaces.
Interlaced Interlaced video comprises alternating fields with either the odd or even lines comprising a video frame. A 1080i video comprises one field of 540 odd-numbered lines followed by one field of 540 even-numbered lines.
Lite variant The variant of the IPs when you turn on lite mode for the Intel FPGA streaming video protocol and which comprises only data packets.
Metapackets Either an image information packet, an end-of-field packet, or an auxiliary control packet.
Progressive Video that is not interlaced. Lines are transmitted in order.
Symbol Pixels are comprised of 1 to 4 symbols. A symbol comprises between 8 and 16 bits of data, representing one color from an RGB triplet (red, blue, green) or a luma or chroma sample from YCbCr pixels, or some other color space component.
Undefined behavior If an IP experiences a stimulus that falls outside of its design parameters, its behavior is unspecified. The IP may fail gracefully, or lock-up, or continue working. Intel does not specify the outcome.
VIP Video and image processing. Intel’s previous generation of video processing IPs from the Video and Image Processing Suite.

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