Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Genlock Controller Intel® FPGA IP 23. Generic Crosspoint Intel® FPGA IP 24. Genlock Signal Router Intel® FPGA IP 25. Guard Bands Intel® FPGA IP 26. Interlacer Intel® FPGA IP 27. Mixer Intel® FPGA IP 28. Pixels in Parallel Converter Intel® FPGA IP 29. Scaler Intel® FPGA IP 30. Stream Cleaner Intel® FPGA IP 31. Switch Intel® FPGA IP 32. Tone Mapping Operator Intel® FPGA IP 33. Test Pattern Generator Intel® FPGA IP 34. Video Frame Buffer Intel® FPGA IP 35. Video Streaming FIFO Intel® FPGA IP 36. Video Timing Generator Intel® FPGA IP 37. Warp Intel® FPGA IP 38. Design Security 39. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 3D LUT Intel® FPGA IP x
8.1. About the 3D LUT Intel® FPGA IP 8.2. 3D LUT IP Parameters 8.3. 3D LUT IP Block Description 8.4. 3D LUT IP Registers 8.5. 3D LUT IP Software API
8.1. About the 3D LUT Intel® FPGA IP x
8.1.1. 3D LUT IP Features 8.1.2. 3D LUT IP Performance IP and Resource Information
8.3. 3D LUT IP Block Description x
8.3.1. 3D LUT IP Interfaces 8.3.2. 3D LUT IP Latency
9. AXI-Stream Broadcaster Intel® FPGA IP x
9.1. About the AXI-Stream Broadcaster IP 9.2. AXI-Stream Broadcaster IP Parameters 9.3. AXI-Stream Broadcaster IP Interfaces
9.1. About the AXI-Stream Broadcaster IP x
9.1.1. AXI-Stream Broadcaster IP Features 9.1.2. AXI-Stream Broadcaster IP Performance and Resources
10. Chroma Key Intel® FPGA IP x
10.1. About the Chroma Key IP 10.2. Chroma Key IP Parameters 10.3. Chroma Key IP Interfaces 10.4. Chroma Key Replacement 10.5. Chroma Key IP Registers 10.6. Chroma Key IP Software API
10.1. About the Chroma Key IP x
10.1.1. Chroma Key IP Performance and Resources
11. Chroma Resampler Intel® FPGA IP x
11.1. About the Chroma Resampler IP 11.2. Chroma Resampler IP Parameters 11.3. Chroma Resampler IP Functional Description 11.4. Chroma Resampler IP Registers 11.5. Chroma Resampler IP Software API
11.1. About the Chroma Resampler IP x
11.1.1. Chroma Resampler Performance and Resources
11.3. Chroma Resampler IP Functional Description x
11.3.1. Chroma Resampler IP Interfaces
12. Clipper Intel® FPGA IP x
12.1. About the Clipper IP 12.2. Clipper IP Parameters 12.3. Clipper IP Interfaces 12.4. Clipper IP Registers 12.5. Clipper IP Software API
12.1. About the Clipper IP x
12.1.1. Clipper IP Performance and Resources
13. Clocked Video Input Intel® FPGA IP x
13.1. About the Clocked Video Input IP 13.2. Initializing the Clocked Video Input IP 13.3. Clocked Video Input IP Parameters 13.4. Clocked Video Input IP Interfaces 13.5. Clocked Video Input IP Registers 13.6. Clocked Video Input IP Software API
13.1. About the Clocked Video Input IP x
13.1.1. Clocked Video Input IP Features 13.1.2. Clocked Video Input IP Performance and Resources
14. Clocked Video to Full-Raster Converter Intel® FPGA IP x
14.1. About the Clocked Video to Full-Raster Converter IP 14.2. Clocked Video to Full-Raster Converter Parameters 14.3. Clocked Video to Full-Raster Converter Block Description 14.4. Clocked Video Converter to Full-Raster IP Registers
14.1. About the Clocked Video to Full-Raster Converter IP x
14.1.1. Clocked Video to Full-Raster Converter Features 14.1.2. Clocked Video to Full-Raster Converter Performance and Resources
14.3. Clocked Video to Full-Raster Converter Block Description x
14.3.1. Clocked Video to Full-Raster Converter Interfaces
15. Clocked Video Output Intel® FPGA IP x
15.1. About the Clocked Video Output IP 15.2. Clocked Video Output IP Parameters 15.3. Clocked Video Output IP Functional Description 15.4. Clocked Video Output IP Interfaces 15.5. Clocked Video Output IP Registers 15.6. Clocked Video Output IP Software API
15.1. About the Clocked Video Output IP x
15.1.1. Clocked Video Output IP Performance and Resources 15.1.2. Clocked Video Output IP Features
16. Color Space Converter Intel® FPGA IP x
16.1. About the Color Space Converter IP 16.2. Color Space Converter IP Parameters 16.3. Color Space Converter IP Functional Description 16.4. Color Space Converter IP Registers 16.5. Color Space Converter IP Software API
16.1. About the Color Space Converter IP x
16.1.1. Color Space Converter IP Features 16.1.2. Color Space Converter IP Performance and Resources
16.3. Color Space Converter IP Functional Description x
16.3.1. Color Space Converter IP Interfaces
17. Deinterlacer Intel® FPGA IP x
17.1. About the Deinterlacer IP 17.2. Deinterlacer Parameters 17.3. Deinterlacer Interfaces 17.4. Deinterlacer Registers 17.5. Deinterlacer IP Software API
17.1. About the Deinterlacer IP x
17.1.1. Deinterlacer Performance and Resources
18. FIR Filter Intel® FPGA IP x
18.1. About the FIR Filter 18.2. FIR Filter Parameters 18.3. FIR Filter IP Operation 18.4. FIR Filter Interfaces 18.5. FIR Filter Registers 18.6. FIR Filter IP Software API
18.1. About the FIR Filter x
18.1.1. FIR Filter IP Performance and Resources
18.3. FIR Filter IP Operation x
18.3.1. FIR Filter Processing 18.3.2. FIR Filter Precision 18.3.3. FIR Coefficient Specification 18.3.4. FIR Filter Symmetry 18.3.5. Result to Output Data Type Conversion
18.3.4. FIR Filter Symmetry x
18.3.4.1. No Symmetry 18.3.4.2. Horizontal Symmetry 18.3.4.3. Vertical Symmetry 18.3.4.4. Horizontal and Vertical Symmetry 18.3.4.5. Diagonal Symmetry
19. Frame Cleaner Intel® FPGA IP x
19.1. About the Frame Cleaner IP 19.2. Frame Cleaner IP Parameters 19.3. Frame Cleaner IP Functional Description 19.4. Frame Cleaner IP Interfaces 19.5. Frame Cleaner IP Registers 19.6. Frame Cleaner IP Software API
19.1. About the Frame Cleaner IP x
19.1.1. Frame Cleaner IP Performance and Resources
20. Full-Raster to Clocked Video Converter Intel® FPGA IP x
20.1. About the Full-Raster to Clocked Video Converter 20.2. Full Raster to Clocked Video Converter Parameters 20.3. Full-Raster to Clocked Video Converter Block Description 20.4. Full-Raster to Clocked Video Converter Registers
20.1. About the Full-Raster to Clocked Video Converter x
20.1.1. Full-Raster to Clocked Video Converter Features 20.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
20.3. Full-Raster to Clocked Video Converter Block Description x
20.3.1. Full Raster to Clocked Video Converter Interfaces
21. Full-Raster to Streaming Converter Intel® FPGA IP x
21.1. About the Full-Raster to Streaming Converter IP 21.2. Full-Raster to Streaming Converter Parameters 21.3. Full-Raster to Streaming Converter Block Description
21.1. About the Full-Raster to Streaming Converter IP x
21.1.1. Full-Raster to Streaming Converter Features 21.1.2. Full-Raster to Streaming Converter Performance and Resources
21.3. Full-Raster to Streaming Converter Block Description x
21.3.1. Full-Raster to Streaming Converter Interfaces
22. Genlock Controller Intel® FPGA IP x
22.1. About the Genlock Controller IP 22.2. Genlock Controller IP Parameters 22.3. Genlock Controller IP Functional Description 22.4. Using Genlock Controller IP Software 22.5. Genlock Controller IP Registers 22.6. Genlock Controller IP Software API
22.1. About the Genlock Controller IP x
22.1.1. Genlock Controller IP Performance and Resources
22.3. Genlock Controller IP Functional Description x
22.3.1. Genlock Controller IP Interfaces
22.4. Using Genlock Controller IP Software x
22.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N) 22.4.2. Locking to Reference Clock N (from Genlock Controller IP free running) 22.4.3. Setting the VCXO hold over 22.4.4. Restarting the Genlock Controller IP 22.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old) 22.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa) 22.4.7. Disturbing a Reference Clock (a cable pull)
23. Generic Crosspoint Intel® FPGA IP x
23.1. About the Generic Crosspoint IP 23.2. Generic Crosspoint IP Parameters 23.3. Generic Crosspoint IP Interfaces 23.4. Generic Crosspoint IP Registers 23.5. Generic Crosspoint IP Software API
23.1. About the Generic Crosspoint IP x
23.1.1. Generic Crosspoint IP Features 23.1.2. Generic Crosspoint Performance and Resources
24. Genlock Signal Router Intel® FPGA IP x
24.1. About the Genlock Signal Router IP 24.2. Genlock Signal Router IP Parameters 24.3. Genlock Signal Router IP Interfaces 24.4. Genlock Signal Router IP Registers 24.5. Genlock Signal Router IP Software API
24.1. About the Genlock Signal Router IP x
24.1.1. Genlock Signal Router IP Features 24.1.2. Genlock Signal Router IP Performance and Resources
25. Guard Bands Intel® FPGA IP x
25.1. About the Guard Bands IP 25.2. Guard Bands IP Parameters 25.3. Guard Bands IP Interfaces 25.4. Guard Bands IP Registers 25.5. Guard Bands IP Software API
25.1. About the Guard Bands IP x
25.1.1. Guard Bands IP Performance and Resources
26. Interlacer Intel® FPGA IP x
26.1. About the Interlacer IP 26.2. Interlacer IP Parameters 26.3. Interlacer IP Functional Description 26.4. Interlacer IP Registers 26.5. Interlacer IP Software API
26.1. About the Interlacer IP x
26.1.1. Interlacer IP Performance and Resources
26.3. Interlacer IP Functional Description x
26.3.1. Interlacer IP Interfaces
27. Mixer Intel® FPGA IP x
27.1. About the Mixer IP 27.2. Mixer IP Parameters 27.3. Mixer IP Functional Description 27.4. Mixer IP Registers 27.5. Mixer IP Software API
27.1. About the Mixer IP x
27.1.1. Mixer IP Performance and Resources
27.3. Mixer IP Functional Description x
27.3.1. Mixer IP Interfaces
28. Pixels in Parallel Converter Intel® FPGA IP x
28.1. About the Pixels in Parallel Converter IP 28.2. Pixels in Parallel Converter IP Parameters 28.3. Pixels in Parallel Converter Interfaces 28.4. Pixels in Parallel Converter Registers 28.5. Pixels in Parallel Converter IP Software API
28.1. About the Pixels in Parallel Converter IP x
28.1.1. Pixels in Parallel Converter IP Performance and Resources
29. Scaler Intel® FPGA IP x
29.1. About the Scaler 29.2. Scaler IP Parameters 29.3. Scaler IP Functional Description 29.4. Scaler IP Registers 29.5. Scaler IP Software API
29.1. About the Scaler x
29.1.1. Scaler IP Performance and Resources
29.2. Scaler IP Parameters x
29.2.1. Scaler Maximum Resolution
29.3. Scaler IP Functional Description x
29.3.1. Coefficient Selection 29.3.2. Coefficient Quantization 29.3.3. Filter Behavior at Edge Boundaries 29.3.4. Partial Frame Scaling 29.3.5. 422 and 420 Chroma Sampled Data Scaling 29.3.6. Scaler IP Interfaces
29.3.1. Coefficient Selection x
29.3.1.1. Updating Scaler IP Runtime Coefficients
30. Stream Cleaner Intel® FPGA IP x
30.1. About the Stream Cleaner IP 30.2. Stream Cleaner IP Parameters 30.3. Stream Cleaner IP Functional Description
30.1. About the Stream Cleaner IP x
30.1.1. Stream Cleaner IP Performance and Resources
30.3. Stream Cleaner IP Functional Description x
30.3.1. Stream Cleaner IP Interfaces
31. Switch Intel® FPGA IP x
31.1. About the Switch IP 31.2. Switch IP Parameters 31.3. Switch IP Functional Description 31.4. Switch IP Registers 31.5. Switch IP Software API
31.1. About the Switch IP x
31.1.1. Switch IP Performance and Resources
31.3. Switch IP Functional Description x
31.3.1. Switch IP Latency 31.3.2. Switch IP Interfaces
32. Tone Mapping Operator Intel® FPGA IP x
32.1. About the Tone Mapping Operator IP 32.2. TMO IP Parameters 32.3. TMO IP Block Description 32.4. TMO IP Registers 32.5. TMO IP Software API
32.1. About the Tone Mapping Operator IP x
32.1.1. TMO IP Features 32.1.2. TMO IP Performance and Resource Utilization
32.3. TMO IP Block Description x
32.3.1. TMO IP Interfaces 32.3.2. TMO IP Latency
33. Test Pattern Generator Intel® FPGA IP x
33.1. About the Test Pattern Generator IP 33.2. Test Pattern Generator IP Parameters 33.3. Test Pattern Generator IP Functional Description 33.4. Test Pattern Generator IP Registers 33.5. Test Pattern Generator IP Software API
33.1. About the Test Pattern Generator IP x
33.1.1. Test Pattern Generator IP Performance and Resources
33.3. Test Pattern Generator IP Functional Description x
33.3.1. Test Pattern Generator IP Interfaces
34. Video Frame Buffer Intel® FPGA IP x
34.1. About the Video Frame Buffer IP 34.2. Video Frame Buffer IP Parameters 34.3. Video Frame Buffer IP Functional Description 34.4. Video Frame Buffer IP Registers 34.5. Video Frame Buffer IP Software API
34.1. About the Video Frame Buffer IP x
34.1.1. Video Frame Buffer Performance and Resources
34.3. Video Frame Buffer IP Functional Description x
34.3.1. Video Frame Buffer IP Interfaces
35. Video Streaming FIFO Intel® FPGA IP x
35.1. About the Video Streaming FIFO IP 35.2. Video Streaming FIFO IP Parameters 35.3. Video Streaming FIFO IP Interfaces
35.1. About the Video Streaming FIFO IP x
35.1.1. Video Streaming FIFO IP Performance and Resources
36. Video Timing Generator Intel® FPGA IP x
36.1. About the Video Timing Generator IP 36.2. Video Timing Generator IP Parameters 36.3. Video Timing Generator IP Functional Description 36.4. Video Timing Generator IP Interfaces 36.5. Video Timing Generator IP Registers 36.6. Video Timing Generator IP Software API
36.1. About the Video Timing Generator IP x
36.1.1. Video Timing Generator IP Features 36.1.2. Video Timing Generator IP Performance and Resources
37. Warp Intel® FPGA IP x
37.1. About the Warp IP 37.2. Warp IP Parameters 37.3. Warp IP Block Description 37.4. Warp IP Registers 37.5. Warp IP Software API
37.1. About the Warp IP x
37.1.1. Warp IP Features 37.1.2. Warp IP Performance and Resource Utilization
37.3. Warp IP Block Description x
37.3.1. Block Cache Tool 37.3.2. Warp IP Interfaces 37.3.3. Warp IP Latency 37.3.4. External Memory for Warp IP
37.5. Warp IP Software API x
37.5.1. Using Warp IP Software 37.5.2. Warp IP Software Code Examples
38. Design Security x
38.1. Memory Subsystems 38.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. AXI-Stream Broadcaster Intel® FPGA IP
10. Chroma Key Intel® FPGA IP
11. Chroma Resampler Intel® FPGA IP
12. Clipper Intel® FPGA IP
13. Clocked Video Input Intel® FPGA IP
14. Clocked Video to Full-Raster Converter Intel® FPGA IP
15. Clocked Video Output Intel® FPGA IP
16. Color Space Converter Intel® FPGA IP
17. Deinterlacer Intel® FPGA IP
18. FIR Filter Intel® FPGA IP
19. Frame Cleaner Intel® FPGA IP
20. Full-Raster to Clocked Video Converter Intel® FPGA IP
21. Full-Raster to Streaming Converter Intel® FPGA IP
22. Genlock Controller Intel® FPGA IP
23. Generic Crosspoint Intel® FPGA IP
24. Genlock Signal Router Intel® FPGA IP
25. Guard Bands Intel® FPGA IP
26. Interlacer Intel® FPGA IP
27. Mixer Intel® FPGA IP
28. Pixels in Parallel Converter Intel® FPGA IP
29. Scaler Intel® FPGA IP
30. Stream Cleaner Intel® FPGA IP
31. Switch Intel® FPGA IP
32. Tone Mapping Operator Intel® FPGA IP
33. Test Pattern Generator Intel® FPGA IP
34. Video Frame Buffer Intel® FPGA IP
35. Video Streaming FIFO Intel® FPGA IP
36. Video Timing Generator Intel® FPGA IP
37. Warp Intel® FPGA IP
38. Design Security
39. Document Revision History for Video and Vision Processing Suite User Guide

22.6. Genlock Controller IP Software API

The IP has a software driver for software control of the IP at run time. The IP does not fit any of the generic device models provided by the Nios II HAL. It exposes a set of dedicated accessors to the control and status registers. The driver structure inherits the base driver structure, so all common methods in Video and Vision Processing IPs Software API are applicable.

intel_vvp_genlock_controller_init

Prototype

uint32_t intel_vvp_genlock_controller_init (intel_vvp_genlock_controller_instance* instance, intel_vvp_core_base base);

Description

Initialization function for a VVP Genlock Controller instance.

Attempts to initialize the fields of the Genlock Controller and its base core

Arguments

instance, pointer to the intel_vvp_ genlock_controller _instance to initialize

base, the accessor for the core (on Nios this is a pointer to the base address of the core)

Returns

kIntelVvpCoreOk success

kIntelVvpCoreVidErr if the v kIntelVvpCoreVidErr if the vendor id of the core is not the IntelFPGA vendor ID.

kIntelVvpCorePidErr if the product id of the core is not the cvi product id

kIntelVvpCoreInstanceErr if the instance parameter is zero (null pointer)

intel_vvp_cvi_get_param_vid_pid

Prototype

uint32_t intel_vvp_genlokc_controller_get_param_vid_pid (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The product ID number

intel_vvp_genlock_controller_get_param_version_number

Prototype

uint32_t intel_vvp_genlock_controller_get_param_version_number (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The IP version number value

intel_intel_vvp_genlock_controller_get_param_cpu_clk_freq_hz

Prototype

uint32_t intel_vvp_genlock_controller_get_param_cpu_clk_freq_hz (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The CPU frequency value in Hertz

intel_vvp_genlock_controller_get_param_num_ref_clks

Prototype

uint32_t intel_vvp_genlock_controller_get_param_num_ref_clks (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The maximum number of reference clock for VCXO tracking

intel_vvp_genlock_controller_get_param_err_val_bits

Prototype

uint32_t intel_vvp_genlock_controller_get_param_err_val_bits (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The number of bits to calculate an error value during a sampling period

intel_vvp_genlock_controller_get_param_clk_div_bits

Prototype

uint32_t intel_vvp_genlock_controller_get_param_clk_div_bits (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The number of bits to generate the PDF clock counter

intel_vvp_genlock_controller_get_param_err_update_bits

Prototype

uint32_t intel_vvp_genlock_controller_get_param_err_update_bits (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The number of bit to generate a PDF sampling window

intel_vvp_genlock_controller_get_param_dac_filter_lsb

Prototype

uint32_t intel_vvp_genlock_controller_get_param_dac_filter_lsb (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The number of LSBs to discard during the error calculation

intel_vvp_genlock_controller_get_param_dac_val_bits

Prototype

uint32_t intel_vvp_genlock_controller_get_param_dac_val_bits (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The number of bit to generate the DAC data output word.

intel_vvp_genlock_controller_get_param_dac_clk_div

Prototype

uint32_t intel_vvp_genlock_controller_get_param_dac_clk_div (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The clock divider factor to generate the PWM output pulse

intel_vvp_genlock_controller_get_param_derivative_en

Prototype

uint32_t intel_vvp_genlock_controller_get_param_derivative_en (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The status for the PID derivative term enable flag

intel_vvp_genlock_controller_get_param_lpf_mode

Prototype

uint32_t intel_vvp_genlock_controller_get_param_lpf_mode (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The LPF mode value

intel_vvp_genlock_controller_get_param_i_gain_mode

Prototype

uint32_t intel_vvp_genlock_controller_get_param_i_gain_mode (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The integral gain mode value

intel_vvp_genlock_controller_get_param_p_gain_mode

Prototype

uint32_t intel_vvp_genlock_controller_get_param_p_gain_mode (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The proportional gain mode value

intel_vvp_genlock_controller_get_param_d_gain_mode

Prototype

uint32_t intel_vvp_genlock_controller_get_param_d_gain_mode (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The derivative gain mode value

intel_vvp_genlock_controller_get_param_lock_cnt_size

Prototype

uint32_t intel_vvp_genlock_controller_get_param_lock_cnt_size (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The number of bit to generate the lock status counter

intel_vvp_genlock_controller_get_param_enable_debug

Prototype

uint32_t intel_vvp_genlock_controller_get_param_enable_debug (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The debug mode value

intel_vvp_genlock_controller_is_rxtx_locked

Prototype

uint32_t intel_vvp_genlock_controller_is_rxtx_locked

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

1 if the bit is asserted, 0 otherwise

intel_vvp_genlock_controller_is_int_overflow

Prototype

uint32_t intel_vvp_genlock_controller_is_int_overflow

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

1 if the bit is asserted, 0 otherwise

intel_vvp_genlock_controller_is_dac_sat

Prototype

uint32_t intel_vvp_genlock_controller_is_dac_sat

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

1 if the bit is asserted, 0 otherwise

intel_vvp_genlock_controller_get_lpf_control_1_enable

Prototype

uint32_t intel_vvp_genlock_controller_get_lpf_control_1_enable

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

the status of the LPF enable flag.

intel_vvp_genlock_controller_get_lpf_control_1_int_rst_dis

Prototype

uint32_t intel_vvp_genlock_controller_get_lpf_control_1_int_rst_dis

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

the status of the LPF automatic reset flag.

intel_vvp_genlock_controller_get_lpf_control_1_lock_loss_conf_en

Prototype

uint32_t intel_vvp_genlock_controller_get_lpf_control_1_lock_loss_conf_en

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

the status of the LPF lock loss confidence counter enable flag.

intel_vvp_genlock_controller_get_lpf_control_1_freq_lock_lsb

Prototype

uint32_t intel_vvp_genlock_controller_get_lpf_control_1_freq_lock_lsb

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

the number of LSBs to ignore during the error calculation.

intel_vvp_genlock_controller_get_lpf_control_1_lock_status_mode

Prototype

uint32_t intel_vvp_genlock_controller_get_lpf_control_1_lock_status_mode

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

the LPF lock operation mode.

intel_vvp_genlock_controller_get_lpf_control_1_i_mode

Prototype

uint32_t intel_vvp_genlock_controller_get_lpf_control_1_i_mode

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

the LPF integral term operation mode.

intel_vvp_genlock_controller_get_lpf_control_1_p_mode

Prototype

uint32_t intel_vvp_genlock_controller_get_lpf_control_1_p_mode

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

the LPF proportional term operation mode.

intel_vvp_genlock_controller_get_lpf_control_1_d_mode

Prototype

uint32_t intel_vvp_genlock_controller_get_lpf_control_1_d_mode

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

the LPF derivative term operation mode.

intel_vvp_genlock_controller_get_lpf_control_1_i_gain_sign_inv

Prototype

uint32_t intel_vvp_genlock_controller_get_lpf_control_1_i_gain_sign_inv

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

the status of the LPF integral term sign flag.

intel_vvp_genlock_controller_get_lpf_control_1_p_gain_sign_inv

Prototype

uint32_t intel_vvp_genlock_controller_get_lpf_control_1_p_gain_sign_inv

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

the status of the LPF proportional term sign flag.

intel_vvp_genlock_controller_get_lpf_control_1_d_gain_sign_inv

Prototype

uint32_t intel_vvp_genlock_controller_get_lpf_control_1_d_gain_sign_inv

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

the status of the LPF derivative term sign flag.

intel_vvp_genlock_controller_get_lpf_control_1_i_gain_frac

Prototype

uint32_t intel_vvp_genlock_controller_get_lpf_control_1_i_gain_frac

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

the status of the DAC enable flag.

intel_vvp_genlock_controller_get_dac_control_op_en

Prototype

uint32_t intel_vvp_genlock_controller_get_dac_control_op_en

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

the status of the DAC enable flag.

intel_vvp_genlock_controller_get_dac_control_data_sel

Prototype

uint32_t intel_vvp_genlock_controller_get_dac_control_data_sel

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

the status of the DAC operation mode.

intel_vvp_genlock_controller_get_dac_control_hold

Prototype

uint32_t intel_vvp_genlock_controller_get_dac_control_hold

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

the status of the DAC hold flag.

intel_vvp_genlock_controller_get_dac_control_op_force_low

Prototype

uint32_t intel_vvp_genlock_controller_get_dac_control_op_force_low

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

the status of the DAC force-low flag.

intel_vvp_genlock_controller_get_dac_control_op_force_high

Prototype

uint32_t intel_vvp_genlock_controller_get_dac_control_op_force_high

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

the status of the DAC force-high flag.

intel_vvp_genlock_controller_get_dac_control_clk_div_disable

Prototype

uint32_t intel_vvp_genlock_controller_get_dac_control_clk_div_disable

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

the status of the DAC clock divider flag.

intel_vvp_genlock_controller_get_dac_control_ob_cpu_value

Prototype

uint32_t intel_vvp_genlock_controller_get_dac_control_ob_cpu_value

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

the DAC offset value.

intel_vvp_genlock_controller_get_pfd_control_enable

Prototype

uint32_t intel_vvp_genlock_controller_get_pfd_control_enable

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

the status of the PFD enable flag.

intel_vvp_genlock_controller_get_pfd_control_ref_clk_sw_sel

Prototype

uint32_t intel_vvp_genlock_controller_get_pfd_control_ref_clk_sw_sel

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

the value of the reference clock for VCXO tracking.

intel_vvp_genlock_controller_get_pfd_control_ref_clk_sw_rst

Prototype

uint32_t intel_vvp_genlock_controller_get_pfd_control_ref_clk_sw_rst

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

the status of the reset associated to each of the reference clocks.

intel_vvp_genlock_controller_get_pfd_control_vcxo_clk_sw_rst

Prototype

uint32_t intel_vvp_genlock_controller_get_pfd_control_vcxo_clk_sw_rst

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

the status of the reset associated to the VCXO clock.

intel_vvp_genlock_controller_get_pfd_control_update_cnt_msbs

Prototype

uint32_t intel_vvp_genlock_controller_get_pfd_control_update_cnt_msbs

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

the value to update the update period counter.

intel_vvp_genlock_controller_get_stat_clk_run

Prototype

uint32_t intel_vvp_genlock_controller_get_stat_clk_run

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

If you assert a bit that indicates the reference clock associated to it is running.

intel_vvp_genlock_controller_get_stat_clk_stop

Prototype

uint32_t intel_vvp_genlock_controller_get_stat_clk_stop

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

If you assert a bit that indicates the reference clock associated to it is not running.

intel_vvp_genlock_controller_get_ref_clk_stop

Prototype

uint32_t intel_vvp_genlock_controller_get_ref_clk_stop

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

the status of the PID output block. If you assert this bit indicates that the PID is not updating this output value because of a reference clock not running.

intel_vvp_genlock_controller_get_pfd_overflow_val

Prototype

uint32_t intel_vvp_genlock_controller_get_pfd_overflow_val

(intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

the status of the error overflow flag.

intel_vvp_genlock_controller_get_lpf_control_2_int_rst_val

Prototype

uint32_t intel_vvp_genlock_controller_get_lpf_control_2_int_rst_val (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The integral accumulator value at reset

intel_vvp_genlock_controller_get_lpf_control_3_i_gain

Prototype

uint32_t intel_vvp_genlock_controller_get_lpf_control_3_i_gain (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The gain to set the integral term for the PID controller

intel_vvp_genlock_controller_get_lpf_control_3_p_gain

Prototype

uint32_t intel_vvp_genlock_controller_get_lpf_control_3_p_gain (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The gain to set the proportional term for the PID controller

intel_vvp_genlock_controller_get_lpf_control_3_d_gain

Prototype

uint32_t intel_vvp_genlock_controller_get_lpf_control_3_d_gain (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

intel_vvp_genlock_controller_get_dac_status_val

Prototype

uint32_t intel_vvp_genlock_controller_get_dac_status_val (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The offset value output to the external VCXO

intel_vvp_genlock_controller_get_clk_dbg_status_1_val

Prototype

uint32_t intel_vvp_genlock_controller_get_clk_dbg_status_1_val (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The frequency value for VCXO clock

intel_vvp_genlock_controller_get_clk_dbg_status_2_val

Prototype

uint32_t intel_vvp_genlock_controller_get_clk_dbg_status_2_val (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The frequency value for reference clock 0

intel_vvp_genlock_controller_get_clk_dbg_status_3_val

Prototype

uint32_t intel_vvp_genlock_controller_get_clk_dbg_status_3_val (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The frequency value for reference clock 1

intel_vvp_genlock_controller_get_clk_dbg_status_4_val

Prototype

uint32_t intel_vvp_genlock_controller_get_clk_dbg_status_4_val (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The frequency value for reference clock 2

intel_vvp_genlock_controller_get_clk_dbg_status_5_val

Prototype

uint32_t intel_vvp_genlock_controller_get_clk_dbg_status_5_val (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The frequency value for reference clock 3

intel_vvp_genlock_controller_get_pfd_dbg_status_val

Prototype

uint32_t intel_vvp_genlock_controller_get_pfd_dbg_status_val (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The PID error

intel_vvp_genlock_controller_get_pfd_tx_rx_ratio_ref0_int_val

Prototype

uint32_t intel_vvp_genlock_controller_get_pfd_tx_rx_ratio_ref0_int_val (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The integer part of the TxRx reference # 0 clock ratio

intel_vvp_genlock_controller_get_pfd_tx_rx_ratio_ref0_frc_val

Prototype

uint32_t intel_vvp_genlock_controller_get_pfd_tx_rx_ratio_ref0_frc_val (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The fractional part of the TxRx reference # 0 clock ratio

intel_vvp_genlock_controller_get_pfd_tx_rx_ratio_ref1_int_val

Prototype

uint32_t intel_vvp_genlock_controller_get_pfd_tx_rx_ratio_ref1_int_val (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The integer part of the TxRx reference # 1 clock ratio

intel_vvp_genlock_controller_get_pfd_tx_rx_ratio_ref1_frc_val

Prototype

uint32_t intel_vvp_genlock_controller_get_pfd_tx_rx_ratio_ref1_frc_val (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The fractional part of the TxRx reference # 1 clock ratio

intel_vvp_genlock_controller_get_pfd_tx_rx_ratio_ref2_int_val

Prototype

uint32_t intel_vvp_genlock_controller_get_pfd_tx_rx_ratio_ref2_int_val (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The integer part of the TxRx reference # 2 clock ratio

intel_vvp_genlock_controller_get_pfd_tx_rx_ratio_ref2_frc_val

Prototype

uint32_t intel_vvp_genlock_controller_get_pfd_tx_rx_ratio_ref2_frc_val (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The fractional part of the TxRx reference # 2 clock ratio

intel_vvp_genlock_controller_get_pfd_tx_rx_ratio_ref3_int_val

Prototype

uint32_t intel_vvp_genlock_controller_get_pfd_tx_rx_ratio_ref3_int_val (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The integer part of the TxRx reference # 3 clock ratio

intel_vvp_genlock_controller_get_pfd_tx_rx_ratio_ref3_frc_val

Prototype

uint32_t intel_vvp_genlock_controller_get_pfd_tx_rx_ratio_ref3_frc_val (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The fractional part of the TxRx reference # 3 clock ratio

intel_vvp_genlock_controller_get_pfd_tx_rx_ratio_vcxo_int_val

Prototype

uint32_t intel_vvp_genlock_controller_get_pfd_tx_rx_ratio_vcxo_int_val (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The integer part of the TxRx VCXO clock ratio

intel_vvp_genlock_controller_get_pfd_tx_rx_ratio_vcxo_frc_val

Prototype

uint32_t intel_vvp_genlock_controller_get_pfd_tx_rx_ratio_vcxo_frc_val (intel_vvp_cvi_instance* instance);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

Returns

The fractional part of the TxRx VCXO clock ratio

intel_vvp_genlock_controller_set_pfd_control_enable

Prototype

int intel_vvp_genlock_controller_set_pfd_control_enable (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_pfd_control_ref_clk_sw_sel

Prototype

int intel_vvp_genlock_controller_set_pfd_control_ref_clk_sw_sel (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_pfd_control_ref_clk_sw_rst

Prototype

int intel_vvp_genlock_controller_set_pfd_control_ref_clk_sw_rst (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_pfd_control_vcxo_clk_sw_rst

Prototype

int intel_vvp_genlock_controller_set_pfd_control_vcxo_clk_sw_rst (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_pfd_control_update_cnt_msbs

Prototype

int intel_vvp_genlock_controller_set_pfd_control_update_cnt_msbs (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_lpf_control_2_int_rst_val

Prototype

int intel_vvp_genlock_controller_set_lpf_control_2_int_rst_val (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_lpf_control_3_i_gain

Prototype

int intel_vvp_genlock_controller_set_lpf_control_3_i_gain (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_lpf_control_3_p_gain

Prototype

int intel_vvp_genlock_controller_set_lpf_control_3_p_gain (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_lpf_control_3_d_gain

Prototype

int intel_vvp_genlock_controller_set_lpf_control_3_d_gain (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_dac_control_op_en

Prototype

int intel_vvp_genlock_controller_set_dac_control_op_en (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_dac_control_data_sel

Prototype

int intel_vvp_genlock_controller_set_dac_control_data_sel (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_dac_control_hold

Prototype

int intel_vvp_genlock_controller_set_dac_control_hold (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_dac_control_op_force_low

Prototype

int intel_vvp_genlock_controller_set_dac_control_op_force_low (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_dac_control_op_force_high

Prototype

int intel_vvp_genlock_controller_set_dac_control_op_force_high (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_dac_control_clk_div_disable

Prototype

int intel_vvp_genlock_controller_set_dac_control_clk_div_disable (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_dac_control_ob_cpu_value

Prototype

int intel_vvp_genlock_controller_set_dac_control_ob_cpu_value (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_lpf_control_1_enable

Prototype

prototype: int intel_vvp_genlock_controller_set_lpf_control_1_enable (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_lpf_control_1_int_rst_dis

Prototype

int intel_vvp_genlock_controller_set_lpf_control_1_int_rst_dis (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_lpf_control_1_lock_loss_conf_en

Prototype

int intel_vvp_genlock_controller_set_lpf_control_1_lock_loss_conf_en (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

argument: instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_lpf_control_1_freq_lock_lsb

Prototype

int intel_vvp_genlock_controller_set_lpf_control_1_freq_lock_lsb (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_lpf_control_1_lock_status_mode

Prototype

int intel_vvp_genlock_controller_set_lpf_control_1_lock_status_mode (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_lpf_control_1_i_mode

Prototype

int intel_vvp_genlock_controller_set_lpf_control_1_i_mode (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_lpf_control_1_p_mode

Prototype

int intel_vvp_genlock_controller_set_lpf_control_1_p_mode (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_lpf_control_1_d_mode

Prototype

int intel_vvp_genlock_controller_set_lpf_control_1_d_mode (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_lpf_control_1_i_gain_sign_inv

Prototype

int intel_vvp_genlock_controller_set_lpf_control_1_i_gain_sign_inv (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_lpf_control_1_p_gain_sign_inv

Prototype

int intel_vvp_genlock_controller_set_lpf_control_1_p_gain_sign_inv (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_lpf_control_1_d_gain_sign_inv

Prototype

int intel_vvp_genlock_controller_set_lpf_control_1_d_gain_sign_inv (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_lpf_control_1_i_gain_frac

Prototype

int intel_vvp_genlock_controller_set_lpf_control_1_i_gain_frac (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_lpf_control_1_rst_dac_sat_latch

Prototype

int intel_vvp_genlock_controller_set_lpf_control_1_rst_dac_sat_latch (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_pfd_tx_rx_ratio_ref0_frc_val

Prototype

int intel_vvp_genlock_controller_set_pfd_tx_rx_ratio_ref0_frc_val (intel_vvp_cvi_instance* instance, float in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_pfd_tx_rx_ratio_ref0_int_val

Prototype

int intel_vvp_genlock_controller_set_pfd_tx_rx_ratio_ref0_int_val (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_pfd_tx_rx_ratio_ref1_frc_val

Prototype

int intel_vvp_genlock_controller_set_pfd_tx_rx_ratio_ref1_frc_val (intel_vvp_cvi_instance* instance, float in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_pfd_tx_rx_ratio_ref1_int_val

Prototype

int intel_vvp_genlock_controller_set_pfd_tx_rx_ratio_ref1_int_val (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_pfd_tx_rx_ratio_ref2_frc_val

Prototype

int intel_vvp_genlock_controller_set_pfd_tx_rx_ratio_ref2_frc_val (intel_vvp_cvi_instance* instance, float in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_pfd_tx_rx_ratio_ref2_int_val

Prototype

int intel_vvp_genlock_controller_set_pfd_tx_rx_ratio_ref2_int_val (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_pfd_tx_rx_ratio_ref3_frc_val

Prototype

int intel_vvp_genlock_controller_set_pfd_tx_rx_ratio_ref3_frc_val (intel_vvp_cvi_instance* instance, float in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_pfd_tx_rx_ratio_ref3_int_val

Prototype

int intel_vvp_genlock_controller_set_pfd_tx_rx_ratio_ref3_int_val (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_pfd_tx_rx_ratio_vcxo_frc_val

Prototype

int intel_vvp_genlock_controller_set_pfd_tx_rx_ratio_vcxo_frc_val (intel_vvp_cvi_instance* instance, float in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

intel_vvp_genlock_controller_set_pfd_tx_rx_ratio_vcxo_int_val

Prototype

int intel_vvp_genlock_controller_set_pfd_tx_rx_ratio_vcxo_int_val (intel_vvp_cvi_instance* instance, uint32_t in_val);

Arguments

instance, pointer to the intel_vvp_genlock_controller_instance

in_val, the input reference value

Returns

kIntelVvpGenlocControllerOk, otherwise kIntelVvpGenlockControllerInstanceErr

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