Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 4/03/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Genlock Controller Intel® FPGA IP 23. Generic Crosspoint Intel® FPGA IP 24. Genlock Signal Router Intel® FPGA IP 25. Guard Bands Intel® FPGA IP 26. Interlacer Intel® FPGA IP 27. Mixer Intel® FPGA IP 28. Pixels in Parallel Converter Intel® FPGA IP 29. Scaler Intel® FPGA IP 30. Stream Cleaner Intel® FPGA IP 31. Switch Intel® FPGA IP 32. Tone Mapping Operator Intel® FPGA IP 33. Test Pattern Generator Intel® FPGA IP 34. Video Frame Buffer Intel® FPGA IP 35. Video Streaming FIFO Intel® FPGA IP 36. Video Timing Generator Intel® FPGA IP 37. Warp Intel® FPGA IP 38. Design Security 39. Document Revision History for Video and Vision Processing Suite User Guide

36.2. Video Timing Generator IP Parameters

The IP offers compile-time parameters. The IP GUI separates the compile-time parameters into four tabs. After you build the IP, you cannot change the build parameters. However, you can change all other parameters using the processor interface.

These parameters are fixed at build time and can only be changed by recompiling the IP.

Table 645.  Build Parameters
  Allowed Range Description
Video Settings
Number of pixels in parallel 1 to 8 Select the number of pixels in parallel
Number of color planes 1 to 4 Select the number of color planes per pixel
Bits per color sample 6 to 16 Select the number of bits per color sample
Output Type AXI4-S FR or CV Select the type of output bus.
AXI4-S FR interface TREADY 89 True or False

Select True to include the tReady signal in the full-raster interface

Select False to remove the tReady signal

CV Timing Signals 90 Sync, Blank, or Both Select which timing signals are included on the output CV bus.
Control Settings
Memory-Mapped Control Interface True or False

Select True to enable the processor interface and associated signals.

When False, the IP removes the processor interface, and all processor registers use default values

Frequency of CPU Clock 91 1 to 1000000000 The frequency, in Hz, of the processor clock.
General Settings
Timing Word Alignment

Any

or

PIP-Aligned Only

Select Any and there is no restriction on raster dimensions versus the number of pixels in parallel.

When PIP-Aligned Only, all timing parameters must be integer multiples of the pixels in parallel value.

Hard frame lock support True or False

Select True to turn on hard frame lock.

When False, the IP removes all frame lock support.

Soft frame lock support True or False

Select True to enable soft frame lock support. 92

When False, the IP removes soft frame lock support.

Variable refresh rate support True or False

Select True to enable variable refresh rate support

When False, the IP removes support for variable refresh rate

Horizontal counter bits 4 to 16

The number of binary bits required to represent the maximum width of raster.

For example, for a 4096 wide, set to 13.

Vertical counter bits 4 to 16

The number of binary bits required to represent the maximum height of raster.

For example, for a 2048 high raster, set to 12.

Number of pulses 0 to 8

The number of additional general-purpose pulses that the IP can produce.

Each additional pulse increases the gate count of this IP.

If 0, the Default Pulse Configuration GUI is off.

Figure 83. Build Parameters GUI
Table 646.   Default Mode Configuration

The Default Mode Configuration parameters apply to the IP when the IP is reset. You can change them during run time using the processor Interface, without recompiling the IP.

  Allowed Range Description
Blanking Type Blank or Sync

Set the style of h and v timing signals on the output.

In full-raster variants, the SYNC MODE bit of the full-raster control word is set to ‘1’ to indicate blank style timing and ‘0’ to indicate sync style.

If blank style is selected for a clocked video interface, the IP drives only the hBlank and vBlank signals.

If sync style is selected for a clocked video interface, the IP drives only the clocked video hSync and CV vSync signals.

Black Value, color plane 0 0 to 65535 The initial value of “black” for this color plane
Black Value, color plane 1 93 0 to 65535 The initial value of “black” for this color plane
Black Value, color plane 2 93 0 to 65535 The initial value of “black” for this color plane
Black Value, color plane 3 93 0 to 65535 The initial value of “black” for this color plane
Frame lock mode

Freerunning

Frame Lock

Variable Refresh Rate

The initial style of frame lock. For Frame Lock and Variable Refresh Rate, you must turn on the appropriate Build Parameters.
Soft frame lock 94 True or False Select True, for a soft frame lock. Select False for the hard frame lock.
Frame start signal type 95 Pulse or Toggle

If you select Pulse, the IP processes the frame start input signal as a pulse. The IP uses the rising edge of the signal to indicate the start of a frame.

If you select Toggle, the IP processes the frame start input signal as a toggle and the IP uses both edges of the signal to indicate the start of a frame.

Frame start max allowed jitter 96 0 to 127

The number of video clock cycles either side of the position of the expected start of frame where an occurrence of the frame start input signal does not cause the raster to restart.

If the frame start input signal occurs more than this number of video clock cycles from the point where it is expected, the IP restarts the output raster.

Soft lock frame start ignore 0 to 127

When you select True for Soft frame lock, this parameter specifies the number of lines where the frame start input signal is ignored.

Unused when you turn off soft lock.

Soft lock frame start adjust 97 0 to 127

When you select True for Soft frame lock, this parameter specifies the total number of lines used for soft lock, including the ignore lines.

Unused when you select false for Soft frame lock.

VRR Line Mode 98 True or False

If you select Variable Refresh Rate for Frame Lock Mode and select True for this parameter, the IP continues to produce whole lines of blanking after it produces the active pixels until it detects the frame start input signal is detected.

If you select Variable Refresh Rate for Frame Lock Mode and select False for this parameter, the IP stops producing a raster when the last active line of a frame completes. The IP resumes output when it detects the frame start input signal.

Unused if you do not select Variable Refresh for Frame Lock Mode.

Figure 84. Default Mode Configuration GUI
Table 647.   Default Timing Configuration

The Default Timing Configuration parameters apply to the IP when the IP is reset. You can change them at run time using the processor Interface, without recompiling the IP.

Parameter Allowed Range 99 100 Description
Dimensions
Default value for HRESET 0 to Hmax

When you select Frame lock for Frame Lock Mode, this parameter is the horizontal coordinate where the IP expects the frame start input signal.

Unused if frame lock is off.

Default value for VRESET 0 to Vmax

When you select Frame lock for Frame Lock Mode, this parameter is the vertical coordinate where the frame start input signal is expected.

Unused if frame lock is off.

Default value for HTOTAL 0 to Hmax The width of the current raster, in pixels.
Default value for VTOTAL 0 to Vmax The width of the current raster, in pixels.
Blank Timing
Default value for HB_END 0 to Hmax First pixel of active video after horizontal blanking. Blanking always starts on pixel 0.
Default value for V1B_START 0 to Vmax First line of vertical blanking for field 1 (if interlaced) and progressive frames.
Default value for V1B_END 0 to Vmax First line of active video after vertical blanking for field 1 (if interlaced) and progressive frames.
Default value for V2B_START 0 to Vmax First line of vertical blanking for field 2 (if interlaced).
Default value for V2B_END 0 to Vmax First line of active video after vertical blanking for field 2 (if interlaced).
Field Timing
Default value for F1_START 0 to Vmax First line where f=0.
Default value for F2_START 0 to Vmax First line where f=1.
Sync Timing
Default value for HS_START 0 to Hmax First pixel of horizontal sync.
Default value for HS_END 0 to Hmax First pixel after horizontal sync.
Default value for V1S_VSTART 0 to Vmax Vertical coordinate of first pixel of vertical sync for field 1 (if interlaced) and progressive frames.
Default value for V1S_HSTART 0 to Hmax Horizontal coordinate of first pixel of vsync for field 1 (if interlaced) and progressive frames.
Default value for V1S_VEND 0 to Vmax Vertical coordinate of first active pixel after vertical sync for field 1 (if interlaced) and progressive frames.
Default value for V1S_HEND 0 to Hmax Horizontal coordinate of first active pixel after vsync for field 1 (if interlaced) and progressive frames.
Default value for V2S_VSTART 0 to Vmax Vertical coordinate of first pixel of vertical sync for field 2 (if interlaced).
Default value for V2S_HSTART 0 to Hmax Horizontal coordinate of first pixel of vsync for field 2 (if interlaced).
Default value for V2S_VEND 0 to Vmax Vertical coordinate of first active pixel after vertical sync for field 2 (if interlaced).
Default value for V2S_HEND 0 to Hmax Horizontal coordinate of first active pixel after vsync for field 2 (if interlaced).
Figure 85. Default Timing Configuration GUI
Table 648.  Default Pulse Configuration

The Default Pulse Configuration parameters apply to the IP when the IP is reset. You can change them at run time using the processor interface, without recompiling the IP.

Each output has one set of parameters. If the Build Parameter tab Number of Pulses is 0, this GUI is not available.

Parameter Allowed Range Description
Default value for PULSEn_VSTART 0 to Vmax Vertical coordinate of first pixel of pulse
Default value for PULSEn_HSTART 0 to Hmax Horizontal coordinate of first pixel of pulse
Default value for PULSEn_VEND 0 to Vmax Vertical coordinate of first active pixel after pulse
Default value for PULSEn_ HEND 0 to Hmax Horizontal coordinate of first active pixel after pulse
Figure 86. Default Pulse Configuration GUI
89

This parameter is only available when you select AXI4-S FR for Output Type

90

This parameter is only available when you select CV for Output Type

91

This parameter is only available when you select True for Memory-Mapped Control Interface

92

Hard Frame Lock must also be True for correct operation of soft frame lock

93

This parameter is only available if the color plane exists. Refer to the Build Parameter tab Number of color planes

94

This parameter is only available if you select Frame lock for Frame Lock Mode

95

This parameter is only available if you select Frame lock or Variable refresh rate for Frame Lock Mode

96

This parameter is only available if you select Frame lock for Frame Lock Mode

97

This parameter is only available if you select True for Soft Frame Lock

98

This parameter is only available if you select Variable refresh rate for Frame Lock Mode

99

Vmax = (2^ Vertical counter bits) - 1

100

Hmax = (2^ Horizontal counter bits) - 1

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