Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 4/03/2023

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Genlock Controller Intel® FPGA IP 23. Generic Crosspoint Intel® FPGA IP 24. Genlock Signal Router Intel® FPGA IP 25. Guard Bands Intel® FPGA IP 26. Interlacer Intel® FPGA IP 27. Mixer Intel® FPGA IP 28. Pixels in Parallel Converter Intel® FPGA IP 29. Scaler Intel® FPGA IP 30. Stream Cleaner Intel® FPGA IP 31. Switch Intel® FPGA IP 32. Tone Mapping Operator Intel® FPGA IP 33. Test Pattern Generator Intel® FPGA IP 34. Video Frame Buffer Intel® FPGA IP 35. Video Streaming FIFO Intel® FPGA IP 36. Video Timing Generator Intel® FPGA IP 37. Warp Intel® FPGA IP 38. Design Security 39. Document Revision History for Video and Vision Processing Suite User Guide

14.3. Clocked Video to Full-Raster Converter Block Description

The IP passes the pixel and timing data through unmodified. The AXI4-S based streaming full-raster bus encapsulates all the pixel and timing data on a single bus, tData. The clocked video bus is a bundle of multiple single wires for the individual video timing strobes, and a data bus for the pixel data.

The clocked video bus can contain additional sideband signals, such as discrete 16-bit signals for the width and height of the raster. The IP ignores these sideband signals and copies some signals CPU registers. The sideband signals provide backward IO interface compatibility between the IP and legacy Intel clocked video input and clocked video output interfaces.

Figure 33. High-level mapping from the clocked video to full-rasterThe figure shows how mapping is a case of concatenating the discrete signals used by the clocked video interface into a single AXI4-S streaming full-raster tData bus.

The AXI4-S tUser signal cannot be generated automatically from the clocked video timing signals. The tUser is asserted for true pixels (0,0) in the full video raster, but the location of (0,0) relative to the timing strobes varies by video standard. Therefore, you need either a CPU interface to instruct the tUser logic where to place in the raster the tUser, or the IP is restricted to a single video standard.