18.1. About the FIR Filter
The IP is available as full or lite variants. For more information on full and lite, refer to the Intel FPGA Streaming Video Protocol Specification. The FIR filter IP takes input resolution information from image information packets or using the register interface for lite variants.
An Avalon memory-mapped interface allows you to read the running status of the IP and optionally update the filter coefficients at run time. This interface is mandatory for lite variants.