The Interlacer Intel FPGA IP converts streams of progressive frames into streams of alternating F0 and F1 fields by discarding either the odd lines (F0) or the even lines (F1). The output field rate is consequently equal to the input frame rate. The Interlacer Intel FPGA IP is compatible with both the lite and full variants of the Intel FPGA Streaming Video interface protocol.
You can turn on an Avalon memory-mapped control agent interface to control the behavior of the Interlacer IP at run time. You can edit settings in the register map to turn interlacing on and off (progressive passthrough), change the output field order (F0 or F1 first), and reset the interlacing sequence.