Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 12/04/2023

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3.4. Reducing Placement Time

The time required to place a design depends on two factors:
  • The number of ways the logic in your design can be placed in the device.
  • The settings that control the amount of effort required to find a good placement.

You can reduce the placement time by changing the settings for the placement algorithm. If you have enabled a higher performance effort compiler optimization mode, you can try reducing the effort setting and observe how it trades off runtime and quality of results (QoR).

You can also observe the placement of major logic blocks in your design (over multiple compiles) to see whether the major blocks tend to get placed in the same places in the floorplan between the compiles. Suppose major blocks get placed in different places in some compiles. If those placements correlate with good QoR, create Logic Lock regions to ensure the blocks are placed in those regions with good QoR, which should help reduce compile time.

Sometimes there is a trade-off between placement time and routing time. Routing time can increase if the placer does not run long enough to find a good placement. When you reduce placement time, ensure that it does not increase routing time and negate the overall time reduction.