Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 12/04/2023
Public
Document Table of Contents

2.18. Design Compilation Revision History

This document has the following revision history.
Document Version Intel® Quartus® Prime Version Changes
2023.12.04 23.4
  • Enhanced the Compiler Optimization Modes topic with additional information.
  • Updated file properties image in Registering the SDC-on-RTL SDC File and Using SDC-on-RTL Features.
  • In Design Synthesis, added information about converting .bdf to .v or .vhd file, and updated the image.
  • Renamed DNI-Based Compilation Flow as Analysis & Elaboration Flow.
  • Added information about Early Timing Analysis flow in Compilation Overview.
  • Reorganized DNI-Based Analysis & Elaboration Flow and Early Timing Analysis After Design Synthesis sections.
  • Renamed DNI-Based Node Finder as Using the Node Finder
  • Added an image for Property Viewer showing constraints in Exploring the RTL Analyzer.
  • Reorganized most of the topics under Design Netlist Infrastructure and moved them into relevant sections of this chapter.
  • Removed the term "DNI" in the title and content of the following topics:
    • Use Case Examples
    • Scripting Routine Tasks Using Tcl Commands
    • Traversing the Design Netlist Using Tcl Commands
  • Revised the information and image in Design Synthesis.
  • Added information about SDC-on-RTL file in Running Synthesis.
  • Revised the image, added a note for "Parameter Settings by Entity Instance" and added information about SDC constraints in Viewing Synthesis Reports.
  • Revised the existing information in Concurrent Analysis During Synthesis or Fitting.
  • Added a note about version compatibility in Importing a Version-Compatible Compilation Database, and Exporting a Design Partition.
  • Renamed the topic Compilation Monitoring as Compilation Monitoring Mode and revised the topic entirely.
  • Revised Enable Intermediate Fitter Snapshots with additional information.
  • Added Preparing for Design Synthesis.
  • Removed Early Timing Analysis After Design Synthesis and merged its information with Post-Synthesis Static Timing Analysis (STA).
2023.10.02 23.3
  • Enhanced the instructions and removed "Beta" in Design Netlist Infrastructure and Exploring the RTL Analyzer.
  • Made minor revisions to the description in Object Set Console.
  • Updated "Viewing Unbundled Instances" section in Bundled Instances.
  • Completely revised the instructions in Early Timing Analysis After Design Synthesis.
  • Made minor updates to Synopsys* Design Constraint (SDC) on RTL.
  • Completely updated "RTL Analyzer" section and added additional information about Constraints viewer in Inspecting SDC-on-RTL Constraints.
  • Added the following topics
    • Entity-Based SDC-on-RTL
    • Using SDC-on-RTL Features
    • DNI-Based Node Finder
  • Updated the commands and replaced SYN_SDC_FILE with SDC_FILE -read_during_post_syn_and_not_post_fit_timing_analysis in Post-Synthesis Static Timing Analysis (STA).
  • Replaced SYN_SDC_FILE in Types of SDC Files Used in the Intel® Quartus® Prime Software.
  • Reorganized the topics in the Design Compilation chapter per the DNI-based compilation dashboard.
  • Updated the compilation dashboard image in the following topics:
    • Using the Compilation Dashboard
    • Concurrent Analysis During Synthesis or Fitting
    • Step 1: Run Register Retiming
    • Step 3: Run Fast Forward Compile
    • Fast Forward Compile By Hierarchy
  • Added description for "Number of Congested Nets" column in Global Router Congestion Hotspot Summary Report.
  • Revised the descriptions of optimization modes in Compiler Optimization Modes.
  • Removed the topic Connectivity Tracer.
  • Updated the "Hierarchical Project Structure" image along with its description in Compilation Hierarchy.
2023.04.03 23.1
  • In Design Netlist Infrastructure (Beta), updated the images and added a note about the incompatibilities between classic and DNI compilation flows.
  • In Exploring the RTL Analyzer (Beta), updated the images and improved their clarity.
  • Enhanced the Sweep Hints Viewer topic with additional information and images.
  • Enhanced the Inspecting SDC-on-RTL Constraints topic with additional information about Object Constraints viewer.
  • Revised the Object Set Console topic entirely.
  • Revised the Auto-hide Unconnected Pins topic entirely.
  • Renamed the topic Early Timing Analysis (Beta) to Early Timing Analysis After Design Synthesis (Beta) and revised the information and images.
  • Enhanced Applying the SDC-on-RTL Constraints with additional information about the Constraint Propagation Report.
  • Updated the images and revised some instructions in Post-Synthesis Static Timing Analysis (STA).
  • Updated the product family name to "Intel Agilex 7."
  • Revised description of Fitter (Finalize) command for latest physical synthesis optimizations.
2022.12.19 22.4
  • Added Filtering.
  • Added Expand Connections.
  • Revised Object Set Console with additional information and images.
2022.09.26 22.3
  • Added Early Timing Analysis (Beta).
  • Added Synopsys* Design Constraint (SDC) on RTL.
  • Added Registering the SDC-on-RTL SDC File.
  • Added Applying the SDC-on-RTL Constraints.
  • Added Managing SDC-on-RTL Constraints.
  • Added Writing Constraints in SDC-on-RTL SDC Files.
  • Added Post-synthesis Static Timing Analysis (STA).
  • Added Types of SDC Files Used in the Intel® Quartus® Prime Software.
  • Added Object Set Console.
  • Added Module Interfaces.
  • Added Connectivity Tracer.
  • Added DNI Use Case Examples.
  • Added Scripting Routine Tasks Using DNI Tcl Commands.
  • Added Traversing the DNI Netlist Using Tcl Commands.
  • Added Viewing Synthesis Dynamic Report.
  • Split the topic Instances Bundling and Auto-hiding Unconnected Pins into separate topics Bundled Instances and Auto-hide Unconnected Pins.
  • Revised Bundled Instances with additional information.
  • Revised images in Exploring the RTL Analyzer and Design Netlist Infrastructure (DNI).
2022.06.21 22.2
  • Added Design Netlist Infrastructure (DNI).
  • Added Exploring the RTL Analyzer.
  • Added Module Interfaces.
  • Added Instances Bundling and Auto-hiding Unconnected Pins.
2022.03.28 22.1
  • Added Compilation Monitoring.
  • Added Global Router Congestion Hotspot Summary Report.
  • Revised Full Compilation Flow.
  • Added Full Compilation Flow with Temporary Optimization Mode.
2022.01.27 21.4
  • Revised Compiler Optimization Modes topic to provide implication details of various modes.
2021.11.03 21.3
  • Made a minor correction in Reusing a Design Partition step 4.
  • Removed the callouts from Creating a Design Partition topic.
2021.10.04 21.3
  • Added Preserving Signals for Monitoring and Debugging topic.
  • Revised Preserving Registers During Synthesis topic for new debugging signal preservation assignments.
  • Revised Viewing Synthesis Reports topic to include new warnings summary reports.
  • Revised Optimization Modes topic to include new optimization modes.
  • Revised VHDL Synthesis Support to include VHDL 2019 support.
  • Revised VHDL Input Settings (Settings Dialog Box) topic to include VHDL 2019 support.
  • Added VHDL-2019 Conditional Analysis topic.
2021.06.21 21.2
  • Added Version-Compatible Compilation Database Support table.
2021.03.29 21.1
  • Added Check Unregistered Ports report to "Validating Timing Constraints with Snapshot Viewer" topic.
  • Updated "Running Snapshot Viewer" topic to indicate the reports that are available after the final snapshot.
  • Removed reference to Rapid Recompile from "Enable Intermediate Filter Snapshots". Support for Rapid Recompile has been removed.
  • Added information to "Using the Compilation Dashboard" to indicate that an interrupted compilation flow can be resumed.
2020.12.14 20.3
  • Corrected typo in "Automatic Gated Clock Conversion" topic.
2020.11.09 20.3
  • Added new "Integrating Other EDA Tools" topic.
  • Added new "Generating a VQM Netlist for Other EDA Tools" topic.
2020.09.28 20.3
  • Added references to ECO Compilation Flow.
  • Removed references to deprecated Early Place Compiler flow.
2020.05.08 20.1
  • Added note about programming file differences between versions to "Compilation Overview" topic.
2020.04.13 20.1
  • Added new "Fast Forward Compile by Hierarchy" topic.
  • Added new assignment to "Fitter Settings Reference" topic..
  • Updated "Verilog and SystemVerilog Synthesis Support" topic for SystemVerilog 2012 support.
  • Added programming file generation support for Intel Agilex devices.
  • Added "Analyzing with the Snapshot Viewer" topic.
  • Added "Running the Snapshot Viewer" topic.
  • Added "Analyzing Failing Paths with Snapshot Viewer" topic.
  • Added "Analyzing Clocking with Snapshot Viewer" topic.
  • Added "Analyzing High Fan-Out Nets with Snapshot Viewer" topic.
  • Added "Analyzing Constraints with Snapshot Viewer" topic.
  • Added "Analyzing Congestion with Snapshot Viewer" topic.
  • Removed Early Place Flow
  • Removed Synthesis Reports figure and table.
  • Removed Heat-Map in Global Signal Visualization Report figure
  • Changed sentence in Fast Forward Compilation to The Fitter automatically retimes registers across RAM and DSP blocks from The Fitter does not automatically retime registers across RAM and DSP blocks.
  • Added more Preservation Level information to Design Partition table.
2019.10.20 19.3
  • Added "Automatic Gated Clock Conversion" topic.
  • Updated "Fractal Synthesis Optimization" and "Enabling or Disabling Fractal Synthesis" topics for automated fractal synthesis for small multipliers.
2019.09.30 19.3
  • Added support for Intel Agilex devices throughout.
  • Added "Global Signal Visualization Report" topic.
  • Added "Global Router Wire Utilization Map" topic.
  • Added "Fast Preserve Option" topic.
  • Reordering of some topics to match design flow.
2019.07.02 19.1
  • Made minor changes in "Fractal Synthesis Optimization" topic.
  • Added a note in step 3a of "Running Synthesis" about enabling fractal synthesis project-wide.
  • Added details about synthesis of PRESERVE_FANOUT_FREE_NODE to "Partial Reconfiguration Design Guidelines."
  • Corrected typo in "Step 3: Run Fast Forward Compile and Hyper-Retiming."
  • Removed "Enabling Timing-Driven Synthesis" topic.
2019.04.01 19.1
  • In "Running Synthesis", removed a step about enabling fractal synthesis project-wide.
  • Updated the "Fractal Synthesis Optimization" topic to describe signed multiplication feature that is now supported by multiplier regularization and arithmetic packing algorithms.
2019.01.03 18.1.0
  • Added snapshot description to "Compilation Overview" and linked to content from "Exporting a Design Partition" and "Exporting a Version-Compatible Compilation Database."
2018.10.19 18.1
  • Described dependency of Rapid Recompile on Enable Intermediate Fitter Snapshots option.
2018.09.24 18.1
  • Described option to enable or disable intermediate Fitter snapshots and updated descriptions of compilation flows and dashboard accordingly.
  • Added "Exporting Compilation Results section and subtopics."
  • Described migration of full chip database in "Exporting a Version-Compatible Compilation Database" topic.
  • Described automated .qdb partition export in "Exporting a Design Partition" topic.
  • Described viewing QDB file metadata in "Viewing Quartus Database File Information."
  • Added "Fractal Synthesis Optimization" topic and updated "Running Synthesis" topic steps for new option.
  • Described new Compiler Optimization Modes and described notice that appears for extended optimization modes added via .qsf.
  • Described new Global Signal Visualization Report.
  • Added "Factors Affecting Compilation Results" topic.
  • Added "Using the Compilation Dashboard" topic.
  • Added description of Enable Auto-Pipelining setting.
  • Added description of Enable Formal Verification Support to "Advanced Synthesis Settings."
  • Added description of Report PR Initial Values as Errors option to "Advanced Synthesis Settings."
  • Added description of Size of the Latch Report option to "Advanced Synthesis Settings."
  • Added description of Size of the PR Initial Conditions Report option to "Advanced Synthesis Settings."
  • Added description of Advanced Physical Synthesis option to "Fitter Settings Reference."
  • Added description of Allow DSP Retiming option to "Fitter Settings Reference."
  • Added description of Allow Early Global Retiming in the Fitter option to "Fitter Settings Reference."
  • Added description of Allow Hyper-Aware Register Chain Area Optimizations in the Fitter option to "Fitter Settings Reference."
  • Added description of Allow RAM Retiming option to "Fitter Settings Reference."
  • Added description of Number of Example Nodes Reported in Fitter Messages option to "Fitter Settings Reference."
  • Added description of Physical Placement Effort option to "Fitter Settings Reference."
  • Added description of Use Checkered Pattern as uninitialized RAM Content option to "Fitter Settings Reference."
  • Updated description of Safe State Machine option for Auto setting.
  • Removed support for Ignore ROW GLOBAL Buffers option.
  • Removed support for Ignore CARRY Buffers option.
  • Removed support for Ignore CASCADE Buffers option.
2018.05.07 18.0
  • Updated Optimization Modes topic to add Compile Time (Aggressive).
  • Relocated concurrent analysis content from the Early Place Flow topic to a new Concurrent Analysis During Synthesis or Fitting topic.
  • Rapid Recompile now supports Intel® Stratix® 10 devices.
  • Enhanced description of Retime Stage Reports.
  • Enhanced description of Retime Stage to include classic register retiming.
Table 57.  Document Revision History

Date

Version

Changes

2017.11.06 17.1.0
  • Added support for Intel® Stratix® 10 Hyper-Aware design flow, Hyper-Retiming, Fast Forward compilation, and Fast Forward Viewer.
  • Added Advanced HyperFlex Settings topic.
  • Added Retiming Restrictions and Workarounds topic.
  • Added statement about Fast Forward compilation support for retiming across RAM and DSP blocks.
  • Added Concurrent Analysis topic.
  • Added Analyzing Fitter Snapshots topic.
  • Added Compilation Dashboard Early Place stage control image.
  • Added Running late_place After Early Place topic.
  • Updated for latest Intel® naming conventions.
2017.05.08 17.0.0
  • Added reference to initial compilation support for Cyclone® 10 GX devices.
  • Described concurrent analysis following Early Place.
  • Updated Compilation Dashboard images for Timing Analyzer, Report, Setting, and Concurrent Analysis controls.
  • Updated description for Auto DSP Block Replacement in Advanced Synthesis Settings.
  • Updated Advanced Fitter Settings for Allow Register Retiming, and for removal of obsolete SSN Optimization option.
  • Added Prevent Register Retiming topic.
  • Added Preserve Registers During Synthesis topic.
  • Removed limitation for Safe State Machine logic option.
  • Added references to Partial Reconfiguration and Block-Based Design Flows.
2016.10.31 16.1.0
  • Implemented Intel re-branding.
  • Described Compiler snapshots and added Analyzing Snapshot Timing topic.
  • Updated project directory structure diagram.
  • Described new Fitter stage menu commands and reports.
  • Added description of Early Place Flow, Implement Flow, and Finalize Flow.
  • Added description of Incremental Optimization in the Fitter.
  • Reorganized order of topics in chapter.
  • Removed deprecated Per-Stage Compilation (Beta) Compilation Flow.
2016.05.03 16.0.0
  • Added description of Fitter Plan, Place and Route stages, reporting, and optimization.
  • Added Per-Stage Compilation (Beta) Compilation Flow
  • Added Compilation Dashboard information.
  • Removed support for Safe State Machine logic option. Encode safe states in RTL.
  • Added Generating Dynamic Synthesis Reports topic.
  • Updated Quartus project directory structure.
2015.11.02 15.1.0
  • First version of document.