Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 12/04/2023
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2.6.3.2. Applying the SDC-on-RTL Constraints

When you perform Analysis & Elaboration on your design, the SDC-on-RTL constraints are read and applied to your elaborated design. If you modify the constraints after Analysis and Elaboration, then you must rerun Analysis and Elaboration.

During the Analysis & Elaboration, quartus_syn reads all SDC-on-RTL SDC files and applies constraints to your design netlist. The order in which the files are listed in the QSF defines the reading order. Once this compilation stage completes, you can inspect the constraints in multiple ways. For more information, refer to Inspecting SDC-on-RTL Constraints and Types of SDC Files Used in the Intel Quartus Prime Software.

The constraints are stored in the internal Intel® Quartus® Prime software netlist. As the compilation flow progresses, various compiler optimizations keep the constraint targets updated. This permits a write once, use anywhere methodology for the constraints.

Once you are satisfied with the constraints, you can run Synthesis from the compilation dashboard. Synthesis converts the elaborated netlist into the node netlist for mapping to device resources. When Synthesis runs, the SDC constraints are processed and propagated by the Synthesis tool and you can review this in the Post-Synthesis Constraints report and Constraint Propagation Report.

Figure 42. Sample Post-Synthesis Constraints Compilation Report

The Constraint Propagation Report shows a chronological history of all changes made to each constraint during the compilation flow. You can observe an entry in the report whenever a constraint is duplicated, moved, or deleted. This report keeps getting updated with entries for modified constraints throughout the compilation flow and includes a reason when a constraint is moved. This report is beneficial for troubleshooting if the constraints changed in a way you did not expect.

Figure 43. Sample Constraint Propagation Report