Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 12/04/2023
Public
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2.8.2.1. Running Snapshot Viewer

You can run the Snapshot Viewer to assist with timing closure and design analysis after running the Plan, Place, Route, or Finalize stages of the Fitter. The Snapshot Viewer allows you to run various analysis tasks from the Flow Navigator to achieve faster timing closure and maximize design performance.
Figure 89. Snapshot Viewer Flow Navigator
Table 21.  Snapshot Viewer Tasks and Commands
Design Task Available at Snapshot Snapshot Viewer Commands
Timing Closure—Analyze Failing Paths Planned, Placed, Routed, Finalized
  • List Top Failing Paths—lists all top failing paths in Snapshot Selections. Select a path to locate in RTL Viewer or Chip Planner.
  • Show Full Timing Path in the Schematic—highlights the path in RTL Viewer for further analysis.
  • Show Full Timing Path in Timing Analyzer—The path loads in the Timing Analyzer for further analysis.
Placed, Routed, Finalized
  • Show Full Timing Path in the Chip View—highlights the path in Chip Planner for further analysis.
Timing Closure—Analyze Clocking

This task is available only for Intel® Stratix® 10 devices.

Placed, Finalized Show Global Clock Visualization—loads the Global Signal Visualization report for the snapshot that allows you to visualize clock sector utilization.
Timing Closure—Analyze High Fanout Nets Placed, Routed, Finalized
  • List High Fanout Nets—lists high fan-out nets in Snapshot Selections. Select a path to locate in RTL Viewer or Chip Planner.
  • Show High Fanout Nets in the Schematic—highlights the paths in RTL Viewer for further analysis.
  • Show High Fanout Nets in the Chip View—highlights the paths in Chip Planner for further analysis.
Timing Closure—Validate Constraints Planned Timing Exceptions—displays the Timing Exceptions Results report that identifies timing paths with hold or removal slack exceeding threshold.
Planned, Placed, Finalized Check Unregistered Ports—displays the Check Unregistered Ports Results report that identifies unregistered partition inputs and paths.
Timing Closure—Analyze Congestion Placed, Routed, Finalized Show Logic Lock Regions with Congestion Heat Map—the Chip Planner displays the Logic Lock regions in a congestion heat map for further analysis.

The following sections describe each analysis task in detail.