Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 12/04/2023
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Document Table of Contents
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2.1. Compilation Overview

The Compiler is modular, allowing you to run only the process that you need. Each Compiler module performs a specific function in the full compilation process. When you run any module, the Compiler runs any prerequisite modules automatically and generates detailed reports at each stage. The Compiler can preserve a "snapshot" of the compilation results after each stage.
Table 1.  Compilation Modules
Compilation Process Description
IP Generation Identifies the status and version of IP components in the project, reports outdated IP that require upgrade, and generates Intel FPGA IPs in the project.
Analysis & Synthesis
  • Analysis & Elaboration—a stage of Analysis & Synthesis that checks for design file and projects errors. It provides different checkpoints or previews (elaborated, instrumented, constrained, and swept) of your design early in the compilation flow and serves as a platform to better analyze your design and improve it.
  • Synthesis—Synthesizes, optimizes, minimizes, and maps design logic to device resources. The "synthesized" snapshot preserves the results of this stage.
Early Timing Analysis Combines Synopsys* Design Constraint (SDC) on RTL and post-synthesis static timing analysis. The SDC-on-RTL allows you to integrate SDC constraints that target nodes using the same names as in your RTL design early in the compilation flow and uses them in the later stages of the Intel® Quartus® Prime compilation. However, you can run the module even without RTL SDCs where you can view the synthesized timing netlist.
Fitter (Place & Route)

Assigns the placement and routing of the design to specific device resources, while honoring timing and placement constraints. The Fitter includes the following stages:

  • Plan—places all periphery elements (such as I/Os and PLLs) and determines a legal clock plan, without core placement or routing. The "planned" snapshot preserves the stage results.
  • Place—places all core elements in a legal location. The "placed" snapshot preserves the stage results.
  • Route—creates all routing between the elements in the design. The "routed" snapshot preserves the stage results.
  • Retime—moves (retimes) existing registers into Hyper-Registers for fine-grained performance improvement. The "retimed" snapshot preserves the stage results. 1
  • Fitter (Finalize)—for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices, converts unnecessary tiles to High-Speed or Low-Power. For Intel® Stratix® 10 and Intel Agilex® 7 devices, performs post-Route fix-up. The "final" snapshot preserves the stage results.
Fast Forward Timing Closure Recommendations Generates detailed reports that estimate performance gains achievable by making specific RTL modifications.
Timing Analysis Analyzes and validates the timing performance of all design logic with the Timing Analyzer.
Power Analysis Optional module that estimates device power consumption. Specify the electrical standard on each I/O cell and the board trace model on each I/O standard in your design.
Assembler Converts the Fitter's placement and routing assignments into a programming image for the FPGA device.
EDA Netlist Writer Generates output files for use in other EDA tools, as Integrating Other EDA Tools describes.
Note:

Each successive release of the Intel® Quartus® Prime software typically includes:

  • Added support for new features in supported FPGA devices.
  • Added support for new devices.
  • Efficiency and performance improvements.
  • Improvements to compilation time and resource use of the design software.

Due to these improvements, different versions of the Intel® Quartus® Prime Pro Edition, Intel® Quartus® Prime Standard Edition, and Intel® Quartus® Prime Lite Edition software can produce different programming files from release to release.

1 Retiming and Fast Forward compilation available only for Intel® Stratix® 10 and Intel Agilex® 7 devices.