Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 12/04/2023
Public
Document Table of Contents
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2.8.2.1.5. Analyzing Congestion with Snapshot Viewer

  1. To run the Place or Route stage of the Fitter, double-click the stage in the Compilation Dashboard.
  2. After the stage completes, click the Snapshot Viewer icon for that stage in the Compilation Dashboard. The Snapshot Viewer opens.
  3. Under Analyze Congestion, double-click Show Logic Lock Regions with Congestion Heat Map. The Chip Planner displays the Logic Lock regions in a congestion heat map for further analysis.
    Figure 99. Show Logic Lock Regions with Congestion Heat Map